PRELIMINARY DATA SHEET
µ
PD44164084, 44164184, 44164364
18M-BIT DDRII SRAM
4-WORD BURST OPERATION
MOS INTEGRATED CIRCUIT
Description
The
µ
PD44164084 is a 2,097,152-word by 8-bit, the
µ
PD44164184 is a 1,048,576-word by 18-bit and the
µ
PD44164364
is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using
full CMOS six-transistor memory cell.
The
µ
PD44164084,
µ
PD44164184 and
µ
PD44164364 integrates unique synchronous peripheral circuitry and a burst
counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K.
These products are suitable for applications which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC FBGA.
Features
•
1.8 ± 0.1 V power supply and HSTL I/O
•
DLL circuitry for wide output data valid window and future frequency scaling
•
Pipelined double data rate operation
•
Common data input/output bus
•
Four-tick burst for reduced address frequency
•
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
•
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability with
µ
s restart
•
User programmable impedence output
•
Fast clock cycle time : 3.0 ns (333 MHz), 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)
•
Simple control logic for easy depth expansion
•
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15822EJ2V0DS00 (2nd edition)
Date Published April 2002 NS CP(K)
Printed in Japan
The mark
shows major revised points.
©
2001
µ
PD44164084, 44164184, 44164364
Ordering Information
Part number
Cycle
Time
ns
Clock
Frequency
MHz
333
300
250
200
167
333
300
250
200
167
333
300
250
200
167
512 K x 36-bit
1 M x 18-bit
2 M x 8-bit
Organization Core Supply
(word x bit)
Voltage
V
1.8 ± 0.1
HSTL
165-pin PLASTIC
FBGA (13 x 15)
I/O
Interface
Package
µ
PD44164084F5-E30-EQ1
µ
PD44164084F5-E33-EQ1
µ
PD44164084F5-E40-EQ1
µ
PD44164084F5-E50-EQ1
µ
PD44164084F5-E60-EQ1
µ
PD44164184F5-E30-EQ1
µ
PD44164184F5-E33-EQ1
µ
PD44164184F5-E40-EQ1
µ
PD44164184F5-E50-EQ1
µ
PD44164184F5-E60-EQ1
µ
PD44164364F5-E30-EQ1
µ
PD44164364F5-E33-EQ1
µ
PD44164364F5-E40-EQ1
µ
PD44164364F5-E50-EQ1
µ
PD44164364F5-E60-EQ1
3.0
3.3
4.0
5.0
6.0
3.0
3.3
4.0
5.0
6.0
3.0
3.3
4.0
5.0
6.0
2
Preliminary Data Sheet M15822EJ2V0DS
µ
PD44164084, 44164184, 44164364
Pin Configurations (Marking Side)
/××× indicates active low signal.
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[
µ
PD44164084F5-EQ1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DD
Q
NC
NC
NC
NC
NC
DQ7
A
4
R, /W
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
/NW1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
/K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
/C
7
NC
/NW0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
/LD
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
A
DQ0 to DQ7
/LD
R, /W
/NW0, /NW1
K, /K
C, /C
ZQ
/DLL
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Nybble Write data select
: Input clock
: Output clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
CQ, /CQ
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: Echo clock
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remark
Refer to
Package Drawing
for the index mark.
Preliminary Data Sheet M15822EJ2V0DS
3
µ
PD44164084, 44164184, 44164364
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[
µ
PD44164184F5-EQ1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DD
Q
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R, /W
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
/BW1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
/K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
/C
7
NC
/BW0
A1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
/LD
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
A0, A1, A
DQ0 to DQ17
/LD
R, /W
/BW0, /BW1
K, /K
C, /C
ZQ
/DLL
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
CQ, /CQ
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: Echo clock
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remark
Refer to
Package Drawing
for the index mark.
4
Preliminary Data Sheet M15822EJ2V0DS
µ
PD44164084, 44164184, 44164364
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[
µ
PD44164364F5-EQ1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DLL
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
NC
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DD
Q
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
4
R, /W
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
/BW2
/BW3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
/K
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
/C
7
/BW1
/BW0
A1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
/LD
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
A0, A1, A
DQ0 to DQ35
/LD
R, /W
/BW0 to /BW3
K, /K
C, /C
ZQ
/DLL
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Output impedance matching
: DLL disable
TMS
TDI
TCK
TDO
CQ, /CQ
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: Echo clock
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remark
Refer to
Package Drawing
for the index mark.
Preliminary Data Sheet M15822EJ2V0DS
5
