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UPD44325084F5-E40Y-EQ2-A

QDR SRAM, 4MX8, 0.45ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165

器件类别:存储    存储   

厂商名称:NEC(日电)

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
NEC(日电)
零件包装代码
BGA
包装说明
LBGA,
针数
165
Reach Compliance Code
compliant
ECCN代码
3A991.B.2.A
最长访问时间
0.45 ns
JESD-30 代码
R-PBGA-B165
JESD-609代码
e1
长度
15 mm
内存密度
33554432 bit
内存集成电路类型
QDR SRAM
内存宽度
8
功能数量
1
端子数量
165
字数
4194304 words
字数代码
4000000
工作模式
SYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
4MX8
封装主体材料
PLASTIC/EPOXY
封装代码
LBGA
封装形状
RECTANGULAR
封装形式
GRID ARRAY, LOW PROFILE
并行/串行
PARALLEL
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
1.51 mm
最大供电电压 (Vsup)
1.9 V
最小供电电压 (Vsup)
1.7 V
标称供电电压 (Vsup)
1.8 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
TIN SILVER COPPER
端子形式
BALL
端子节距
1 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
13 mm
文档预览
DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD44325084, 44325094, 44325184, 44325364
36M-BIT QDR
TM
II SRAM
4-WORD BURST OPERATION
Description
The
μ
PD44325084 is a 4,194,304-word by 8-bit, the
μ
PD44325094 is a 4,194,304-word by 9-bit, the
μ
PD44325184 is a
2,097,152-word by 18-bit and the
μ
PD44325364 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44325084,
μ
PD44325094,
μ
PD44325184 and
μ
PD44325364 integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive
edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
User programmable impedance output
Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
<R>
Operating ambient temperature: Commercial T
A
= 0 to +70°C
Industrial
T
A
= –40 to +85°C
(-E37, -E40, -E50)
(-E40Y, -E50Y)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16784EJ4V0DS00 (4th edition)
Date Published March 2007 NS CP(N)
Printed in Japan
The mark <R> shows major revised points.
2003
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
μ
PD44325084, 44325094, 44325184, 44325364
Ordering Information
(1) Operating Ambient Temperature T
A
= 0 to +70°C
Part number
Cycle
Time
ns
Clock
Frequency
MHz
270
250
200
270
250
200
270
250
200
270
250
200
270
250
200
270
250
200
270
250
200
270
250
200
1M x 36-bit
2M x 18-bit
4M x 9-bit
Lead-free
4M x 8-bit
165-pin PLASTIC
BGA (13 x 15)
1M x 36-bit
2M x 18-bit
4M x 9-bit
4M x 8-bit
165-pin PLASTIC
BGA (13 x 15)
Organization
(word x bit)
Package
Operating
Ambient
Temperature
Commercial
(T
A
= 0 to +70°C)
μ
PD44325084F5-E37-EQ2
μ
PD44325084F5-E40-EQ2
μ
PD44325084F5-E50-EQ2
μ
PD44325094F5-E37-EQ2
μ
PD44325094F5-E40-EQ2
μ
PD44325094F5-E50-EQ2
μ
PD44325184F5-E37-EQ2
μ
PD44325184F5-E40-EQ2
μ
PD44325184F5-E50-EQ2
μ
PD44325364F5-E37-EQ2
μ
PD44325364F5-E40-EQ2
μ
PD44325364F5-E50-EQ2
μ
PD44325084F5-E37-EQ2-A
μ
PD44325084F5-E40-EQ2-A
μ
PD44325084F5-E50-EQ2-A
μ
PD44325094F5-E37-EQ2-A
μ
PD44325094F5-E40-EQ2-A
μ
PD44325094F5-E50-EQ2-A
μ
PD44325184F5-E37-EQ2-A
μ
PD44325184F5-E40-EQ2-A
μ
PD44325184F5-E50-EQ2-A
μ
PD44325364F5-E37-EQ2-A
μ
PD44325364F5-E40-EQ2-A
μ
PD44325364F5-E50-EQ2-A
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
3.7
4.0
5.0
Remarks 1.
QDR Consortium standard package size is 13 x 15 and 15 x 17.
The footprint is commonly used.
2.
Products with -A at the end of the part number are lead-free products.
2
Data Sheet
M16784EJ4V0DS
μ
PD44325084, 44325094, 44325184, 44325364
<R>
(2) Operating Ambient Temperature T
A
= –40 to +85°C
Part number
Cycle
Time
ns
Clock
Frequency
MHz
250
200
250
200
250
200
250
200
250
200
250
200
2M x 18-bit
4M x 9-bit
Lead-free
4M x 8-bit
165-pin PLASTIC
BGA (13 x 15)
2M x 18-bit
4M x 9-bit
4M x 8-bit
165-pin PLASTIC
BGA (13 x 15)
Organization
(word x bit)
Package
Operating
Ambient
Temperature
Industrial
(T
A
= –40 to +85°C)
μ
PD44325084F5-E40Y-EQ2
μ
PD44325084F5-E50Y-EQ2
μ
PD44325094F5-E40Y-EQ2
μ
PD44325094F5-E50Y-EQ2
μ
PD44325184F5-E40Y-EQ2
μ
PD44325184F5-E50Y-EQ2
μ
PD44325084F5-E40Y-EQ2-A
μ
PD44325084F5-E50Y-EQ2-A
μ
PD44325094F5-E40Y-EQ2-A
μ
PD44325094F5-E50Y-EQ2-A
μ
PD44325184F5-E40Y-EQ2-A
μ
PD44325184F5-E50Y-EQ2-A
4.0
5.0
4.0
5.0
4.0
5.0
4.0
5.0
4.0
5.0
4.0
5.0
Remarks 1.
QDR Consortium standard package size is 13 x 15 and 15 x 17.
The footprint is commonly used.
2.
Products with -A at the end of the part number are lead-free products.
Data Sheet
M16784EJ4V0DS
3
μ
PD44325084, 44325094, 44325184, 44325364
Pin Configurations
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44325084]
4M x 8-bit
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DD
Q
NC
NC
D6
NC
NC
Q7
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NW1#
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC
NW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
A
D0 to D7
Q0 to Q7
R#
W#
NW0#, NW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL/PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1.
×××#
indicates active LOW signal.
2.
Refer to
Package Drawing
for the index mark.
3.
2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
2A of this product can also be used as NC.
4
Data Sheet
M16784EJ4V0DS
μ
PD44325084, 44325094, 44325184, 44325364
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44325094]
4M x 9-bit
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DD
Q
NC
NC
D7
NC
NC
Q8
A
4
W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NC
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
R#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
A
D0 to D8
Q0 to Q8
R#
W#
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL/PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1.
×××#
indicates active LOW signal.
2.
Refer to
Package Drawing
for the index mark.
3.
2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
2A of this product can also be used as NC.
Data Sheet
M16784EJ4V0DS
5
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