DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD6221
I
2
C-BUS COMPATIBLE OCTAL 8BIT D/A CONVERTER
DESCRIPTION
The
µ
PD6221 is an 8-bit monolithic CMOS digital-to-analog converter using the R-2R technique. The
µ
PD6221
incorporates an 8-channel digital-to-analog converters and I
2
C-bus compatible interface. The designer needs only
2 signals (Serial Data and Serial Clock) to interface and can use 8-ICs (64-channels) on same bus to control chip-
select terminals.
The
µ
PD6221 incorporates Output CMOS Buffer to achieve wide output voltage range and two reference voltage
terminals.
The
µ
PD6221 is ideal for automatic control for color-television.
FEATURES
• 8-channel 8-bit digital-to-analog converter using the R-2R ladder technique
• I
2
C-bus compatible serial interface (Serial Data and Serial Clock)
• 8-ICs (64-channels) can be connected by chip-select terminals
• Output CMOS Buffer to achieve wide output voltage range
• Two reference voltage
ORDERING INFORMATION
PART NO.
PACKAGE
20-pin plastic DIP (300 mil)
20-pin plastic SOP (300 mil)
µ
PD6221CX
µ
PD6221GS
Caution Purchase of NEC I
2
C components conveys a license under the Philips I
2
C patent Right to use these
components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification
as defined by Philips.
Document No. S10277EJ2V0DS00 (2nd edition)
Date Published November 1998 N CP(K)
Printed in Japan
©
1996
µ
PD6221
BLOCK DIAGRAM
CS0
20
CS1
19
CS2
18
VDD VCC
17
16
AO4
15
AO3
14
AO2
13
AO1
12
VrefU2
11
Chip Select
−
+
−
+
−
+
−
+
R-2RLadder
Address
Decoder
8
I
2
C-Bus
Tran-
ceiver
4
8-bit Latch
8
4
8-bit Latch
3
3
R-2RLadder
R-2RLadder
R-2RLadder
2
8-bit Latch
8-bit Latch
8-bit Latch
2
8-bit Latch
8-bit Latch
8-bit Latch
R-2RLadder
R-2RLadder
R-2RLadder
R-2RLadder
+
−
+
−
+
−
+
−
1
2
3
4
5
6
7
8
9
10
R
SCL
SDA
AO5
AO6
AO7
AO8
VrefL
VrefU1
GND
2
µ
PD6221
PIN CONNECTION DIAGRAM (Top View)
R
1
20
CS0
SCL
2
19
CS1
SDA
3
18
CS2
AO5
4
17
V
DD
AO6
5
16
V
CC
AO7
6
15
AO4
AO8
7
14
AO3
V
ref
L
8
13
AO2
V
ref
U1
9
12
AO1
GND
10
11
V
ref
U2
3
µ
PD6221
PIN CONFIGURATION
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYMBOL
R
SCL
SDA
AO5
AO6
AO7
AO8
V
ref
L
V
ref
U1
GND
V
ref
U2
AO1
AO2
AO3
AO4
V
CC
V
DD
CS2
CS1
CS0
Reset Input
Note
Serial Clock Input
Serial Data Input (Output: acknowledgement signal)
Analog Output Channel 5
Analog Output Channel 6
Analog Output Channel 7
Analog Output Channel 8
GND Side Reference Voltage Input (The current of I
ref
U1 and I
ref
U2 flow out from IC.)
V
CC
Side Reference Voltage Input 1 (The current of I
ref
U1 flows into IC.)
Ground
V
CC
Side Reference Voltage Input 2 (The current of I
ref
U2 flows into IC.)
Analog Output Channel 1
Analog Output Channel 2
Analog Output Channel 3
Analog Output Channel 4
Analog Power Supply
Digital Power Supply
Chip Select 2
Chip Select 1
Chip Select 0
FUNCTION
Note
When the Reset Input (R) is low, Analog Output Data (D0, D1 ··· D7) will be set all 0. And the all Analog
Output will be Zero Scale (1LSB + V
ref
L).
4
µ
PD6221
EQUIVALENT CIRCUIT OF PIN
• Equivalent Circuit of R, CS0, CS1, CS2 Pins
V
DD
R, CS0, CS1, CS2
GND
• Equivalent Circuit of SCL Pin
V
DD
SCL
GND
• Equivalent Circuit of SDA Pin
V
DD
SDA
ACK
GND
5
FPGA/CPLD
