DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD77115, 77115A
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
DESCRIPTION
The
µ
PD77115 and
µ
PD77115A are 16-bit fixed-point digital signal processors (DSP).
The
µ
PD77115 and
µ
PD77115A are RAM based DSP and have the specific circuit for audio application.
Unless otherwise specified, the
µ
PD77115 refers to
µ
PD77115 and 77115A.
For details of the functions of the
µ
PD77115, refer to the following User’s Manuals:
µ
PD77111 Family User’s Manual - Architecture
µ
PD77016 Family User’s Manual - Instructions
: U14623E
: U13116E
FEATURES
•
•
•
Instruction cycle (operating clock)
Memory
• Internal instruction RAM
• Internal data RAM
Peripherals
• Audio serial interface
• Secure Digital (SD) card interface
• 16-bit timer
• 16-bit host interface
• 8-bit port
13.3 ns MIN. (75 MHz MAX.)
11.5K words
×
32 bits
16K words
×
16 bits
×
2 banks
•
Supply voltage
• DSP core voltage
2.0 to 2.7 V (MAX. operation speed 50 MHz)
2.3 to 2.7 V (MAX. operation speed 75 MHz)
• I/O pin voltage
2.7 to 3.6 V
•
Power consumption
TYP. 50 mW (2.0 V, 50 MHz operation)
ORDERING INFORMATION
Part Number
Package
80-pin plastic FBGA (9
×
9)
80-pin plastic TQFP (fine pitch) (12
×
12)
80-pin plastic FBGA (9
×
9)
µ
PD77115F1-CN6
µ
PD77115GK-9EU
µ
PD77115AF1-xxx-CN6
Remark
xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U14867EJ5V0DS00 (5th edition)
Date Published August 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2000, 2004
2
X bus
Y bus
BLOCK DIAGRAM
Peripheral units
Audio serial
interface
Data Sheet U14867EJ5V0DS
Data memory unit
X memory
data
addressing
unit
Y memory
data
addressing
unit
R0 to R7
X memory
Y memory
SD card
interface
DMA bus
Main bus
Port
Program
control unit
Loop control
stack
Instruction
memory
MAC
16 x 16 + 40 -> 40
ALU(40)
BSFT
Host
interface
PC stack
Interrupt
control
Operation unit
CPU control
PLL
Timer
µ
PD77115, 77115A
INT1 to INT4
RESET
WAKEUP
CLKOUT
CLKIN
PLL0 to PLL3
Note
Note
The PLL0 to PLL3 pins are multiplexed with the P4 to P7 pins.
Debug
interface
µ
PD77115, 77115A
FUNCTION PIN GROUPS
+ 2.5 V
+3V
IV
DD
Audio
Serial
Interface
SO
SOEN/LRCLK
SCK/BCLK
SI
SIEN/MCLK
EV
DD
RESET
INT1 to INT4
CLKIN
CLKOUT
(4)
Reset,
Interrupt
Clock
SD Card
Interface
SDDAT
SDCR
SDCLK
WAKEUP
System Control
Port
(8)
P0 to P3,P4/PLL0 to P7/PLL3
(2)
Host
Interface
(16)
HCS
HA0,HA1
HRD
HRE
HWR
HWE
HD0 to HD15
TDO,TICE
TCK,TDI,TMS,TRST
GND
Debug
Interface
(2)
(4)
Remark
The P4 to P7 pins are multiplexed with PLL0 to PLL3 pins.
Data Sheet U14867EJ5V0DS
3
4
Data Sheet U14867EJ5V0DS
DSP FUNCTION LIST
Item
Memory
space
(words
×
bits)
Int. instruction RAM
Int. instruction ROM
Data RAM
(X/Y memory)
Data ROM
(X/Y memory)
Ext. instruction
Ext. data memory (X/Y
memory)
Instruction cycle (at maximum
operating speed)
Multiple
15.3 ns
(65 MHz)
Integer multiple
of
×1
to 8
(external pin)
Peripheral
Serial interface
2 channels
(speech CODEC)
Host interface
General-purpose
port (I/O
programmable)
Timer
None
1 channel
(16-bit resolution)
Others
Supply voltage
−
−
−
DSP core: 2.5 V
I/O pins: 3 V
Package
100-pin TQFP
80-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin TQFP
80-pin FBGA
−
−
SD card I/F
−
2 channels
(16-bit resolution)
SD card I/F
DSP core: 1.5 V
I/O pins: 3 V
161-pin FBGA
144-pin LQFP
8-bit bus
4 bits
8 bits
13.3 ns
(75 MHz)
Integer multiple of
×1
to 16
(mask option)
Integer multiple
of
×1
to 16
(external pin)
1 channel
(audio CODEC)
16-bit bus
16 bits (some are alternative with
host)
2 channels (time-division, audio)
6.25 ns
(160 MHz)
32 K
×
16 each
None
16 K
×
16 each
None
None
8 K
×
16 each
None
1 M
×
16
1 M
×
16 (8 K
×
16, using SD I/F)
8.33 ns
(120 MHz)
None
16 K
×
16 each
32 K
×
16 each
None
32 K
×
16 each
µ
PD77110
35.5 K
×
32
None
24 K
×
16 each
µ
PD77111
1 K
×
32
µ
PD77112
µ
PD77113A
3.5 K
×
32
48 K
×
32
µ
PD77114
µ
PD77115,77115A
11.5 K
×
32
None
16 K
×
16 each
µ
PD77210
31.5 K
×
32
µ
PD77213
15.5 K
×
32
64K
×
32
31.75 K
×
32
3 K
×
16 each
16 K
×
16 each
30 K
×
16 each
18 K
×
16 each
Integer multiple of
×10
to 64
(external pin)
µ
PD77115, 77115A
µ
PD77115, 77115A
PIN CONFIGURATIONS
80-pin plastic fine pitch BGA (9
×
9)
µ
PD77115F1-CN6
µ
PD77115AF1-xxx-CN6
(Bottom View)
9
8
7
6
5
4
3
2
1
J
H
G
F
E
D
C
B
A
A
B
C
D
E
F
G
H
J
(Top View)
Index mark
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
Pin Name
EV
DD
NC
EV
DD
IV
DD
INT2
RESET
TDI
I.C.
I.C.
NC
SI
SDCR
GND
WAKEUP
INT1
TMS
TCK
I.C.
SIEN/MCLK
SCK/BCLK
Pin No.
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
E4
Pin Name
SDDAT
GND
INT3
TRST
TICE
TDO
HA0
SOEN/LRCLK
P5/PLL1
SO
P7/PLL3
SDCLK
INT4
IV
DD
HA1
GND
P6/PLL2
P4/PLL0
GND
P2
Pin No.
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
G4
G5
G6
G7
Pin Name
GND
HWR
EV
DD
CLKOUT
EV
DD
P0
P3
HD9
HD4
HRD
HWE
CLKIN
HCS
P1
HD15
HD14
HD11
HD8
HD5
HD1
Pin No.
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
J1
J2
J3
J4
J5
J6
J7
J8
J9
Pin Name
HRE
EV
DD
GND
EV
DD
HD12
EV
DD
GND
HD2
IV
DD
HD0
GND
NC
GND
HD13
HD10
HD7
HD6
HD3
GND
I.C.
Data Sheet U14867EJ5V0DS
5
