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UT54ACS86-UQAR

XOR Gate, AC Series, 4-Func, 2-Input, CMOS, CDFP14, FP-14

器件类别:逻辑    逻辑   

厂商名称:Cobham PLC

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Cobham PLC
包装说明
DFP, FL14,.3
Reach Compliance Code
unknown
系列
AC
JESD-30 代码
R-CDFP-F14
JESD-609代码
e0
长度
9.525 mm
逻辑集成电路类型
XOR GATE
最大I(ol)
0.0001 A
功能数量
4
输入次数
2
端子数量
14
最高工作温度
125 °C
最低工作温度
-55 °C
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DFP
封装等效代码
FL14,.3
封装形状
RECTANGULAR
封装形式
FLATPACK
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
5 V
Prop。Delay @ Nom-Sup
14 ns
传播延迟(tpd)
14 ns
认证状态
Not Qualified
施密特触发器
NO
筛选级别
MIL-PRF-38535 Class Q
座面最大高度
2.921 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
MILITARY
端子面层
Tin/Lead (Sn/Pb)
端子形式
FLAT
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
总剂量
100k Rad(Si) V
宽度
6.2865 mm
文档预览
UT54ACS86/UT54ACTS86
Radiation-Hardened
Quadruple 2-Input Exclusive OR Gates
FEATURES
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
PINOUTS
14-Pin DIP
Top View
A1
B1
Y1
A2
B2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
DESCRIPTION
The UT54ACS86 and the UT54ACTS86 are quadruple 2-input
exclusive OR gates. The devices perform the Boolean function
Y = A B = AB + AB in positive logic.
An application is as a true/complement element. If one of the
inputs is low, the other input will be reproduced in true form at
the output. If one of the inputs is high, the signal on the other
input will be reproduced inverted at the output.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
INPUTS
A
L
L
H
H
B
L
H
L
H
OUTPUT
Y
L
H
H
L
A2
B2
A3
B3
A4
B4
A1
B1
A1
B1
Y1
A2
B2
Y2
V
SS
14-Lead Flatpack
Top View
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
B4
A4
Y4
B3
A3
Y3
LOGIC DIAGRAM
Y1
LOGIC SYMBOL
A1
B1
A2
B2
A3
B3
A4
B4
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
(11)
=1
(3)
(6)
(8)
Y2
Y3
Y1
Y2
Y3
Y4
Y4
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
57
RadHard MSI Logic
UT54ACS86/UT54ACTS86
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
JC
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
10
1
UNITS
V
V
C
C
C
C/W
mA
W
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
C
Rad-ard MSI Logic
58
UT54ACS86/UT54ACTS86
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V 10%; V
SS
= 0V
6
, -55 C < T
C
< +125 C)
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
I
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100 A
I
OH
= -8.0mA
I
OH
= -100 A
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
= 1MHz @ 0V
= 1MHz @ 0V
15
15
pF
pF
1.8
10
1.6
mW/
MHz
A
mA
-8
mA
.7V
DD
V
DD
- 0.25
-200
8
200
.5V
DD
.7V
DD
-1
1
0.40
0.25
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
A
V
V
OH
V
I
OS
I
OL
mA
mA
59
RadHard MSI Logic
UT54ACS86/UT54ACTS86
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
AC ELECTRICAL CHARACTERISTICS
2
(V
DD
= 5.0V 10%; V
SS
= 0V
1
, -55 C < T
C
< +125 C)
SYMBOL
t
PHL
t
PLH
Data to input
Data to input
PARAMETER
MINIMUM
1
1
MAXIMUM
14
13
UNIT
ns
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
Rad-ard MSI Logic
60
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