Standard Products
RadHard Eclipse FPGA Family (6250 and 6325)
Advanced Data Sheet
December, 2004
www.aeroflex.com/RadHardFPGA
FEATURES
0.25µm, five-layer metal, ViaLink
TM
epitaxial CMOS
process for smallest die sizes
One-time programmable, ViaLink technology for
personalization
150 MHz 16-bit counters, 150 MHz datapaths, 60+ MHz
FIFOs
2.5V core supply voltage, 3.3V I/O supply voltage
Up to 320,000 usable system gates (non-volatile)
I/Os
- Interfaces with 3.3 volt
- PCI compliant with 3.3 volt
- Full JTAG 1149.1 compliant
- Registered I/O cells with individually controlled enables
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Test Method 1019
- Total-dose: 300 krad(Si)
- SEL Immune: >120MeV-cm
2
/mg
- LET
TH
(0.25) MeV-cm
2
/mg:
>42 logic cell flip flops
>64 for embedded SRAM
- Saturated Cross Section (cm2) per bit
5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
Up to 24 dual-port RadHard SRAM modules, organized in
user-configurable 2,304 bit blocks
- 5ns access times, each port independently accessible
- Fast and efficient for FIFO, RAM, and initialized RAM
functions
100% routable with 100% utilization and 100% user fixed
I/O
Variable-grain logic cells provide high performance and
100% utilization
Comprehensive design tools include high quality Verilog/
VHDL synthesis and simulation
QuickLogic IP available for microcontrollers, DRAM
controllers, USART and PCI
Packaged in a 208-pin CQFP, 288 CQFP, 484 CCGA, and
484 CLGA
Standard Microcircuit Drawing 5962-04229
- QML Q and V compliant part
INTRODUCTION
The RadHard Eclipse Field Programmable Gate Array Family
(FPGA) offers up to 320,000 usable system gates including
Dual-Port RadHard SRAM modules. It is fabricated on 0.25µm
five-layer metal ViaLink CMOS process and contains a
maximum of 1,536 logic cells and 24 dual-port RadHard SRAM
modules (see Figure 1 Block Diagram). Each RAM module has
2,304 RAM bits, for a maximum total of 55,300 bits. Please
reference product family comparison chart on page 2.
RAM modules are Dual Port (one asynchronous/synchronous
read port, one write port) and can be configured into one of four
modes (see Figure 2). The RadHard Eclipse FPGA is available
in a 208-pin Cerquad Flatpack, allowing access to 99
bidirectional signal I/O, 1 dedicated clock, 8 programmable
clocks and 16 high drive inputs. Other package options include
a 288 CQFP, 484 CCGA and a 484 CLGA.
Designers can cascade multiple RAM modules to increase the
depth or width allowed in single modules by connecting
corresponding address lines together and dividing the words
between modules (see Figure 3). This approach allows a variety
of address depths and word widths to be tailored to a specific
application.
Aeroflex uses QuickLogic Corporation’s licensed ESP
(Embedded Standard Products) technology. QuickLogic is a
pioneer in the FPGA semiconductor and software tools field.
1
Product Family Comparison
The RadHard Eclipse Field Programmable Gate Array Family consists of the UT6250 and UT6325. The similarities and differences are
summarized in the chart below
.
Features
Device
System
Gates
320,640
Logic
Cells
1,536
Maximum
Logic
Flip Flops Cell Flip
Flops
3,692
3072
RAM
Modules
24
RAM
Bits
55,300
I/O Standards
Clocks
High
Drive
Inputs
16
UT6325
LVTTL,
LVCMOS3, PCI,
GTL+, SSTL2,
SSTL3
LVTTL,
LVCMOS3, PCI,
GTL+, SSTL2,
SSTL3
9
UT6250
248,160
960
2,670
1920
20
46,100
9
16
Radiation
Device
UT6325
UT6250
RadHard
Total Dose
3E5
3E5
LET
TH
(0.25) MeV-cm
2
/mg
>42 logic cell flip flops
>64 embedded SRAM
>42 logic cell flip flops
>64 embedded SRAM
Saturated Cross Section
5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
Latch-up
Immune
>120
>120
Packages
Device
UT6235
UT6250
208 PQFP
99
99
208 CQFP
99
99
280PBGA
163
163
288 CQFP
163
163
484 PBGA
310
250
484 CLGA
310
250
484 CCGA
310
250
2
Embedded RAM Blocks
IP
Maximum
of
24
RadHard
SRAM
Blocks
Fabric
Maximum
of
1,536
High
Speed
Variable
Grain
Logic
Cells
Embedded RAM Blocks
Bidirectional I//O and
High-Drive Inputs
Figure 1. RadHard Eclipse FPGA Block Diagram
3
PRODUCT DESCRIPTION
I/O Pins
(9:0)
(17:0)
WA
WD
WE
WCLK
(1:0)
MODE
RE
RCLK
RA
RD
ASYNCRD
(9:0)
(17:0)
• Up to 310 bi-directional input/output pins, PCI-compliant for
3.3V buses (see Table 4)
• Each bidirectional I/O contains RadHard flip-flops for input,
output, and output enable lines
Distributed Networks
• One, dedicated clock network, hardwired to each logic cell
flip-flop clock pin to minimize skew
• Eight programmable clock networks, accessible from clock
pins or internal logic
Figure 2. RadHard Eclipse FPGA RAM
Software support for the product is available from QuickLogic.
The turnkey QuickWorks
TM
package provides the most com-
plete software solution from design entry to logic synthesis,
place and route, simulation, static timing, and power analysis.
The QuickTools
TM
for Workstations package provides a solu-
tion for designers who use Cadence, Exemplar, Mentor, Synop-
sys, Synplicity, Viewlogic, Veribest or other third-party tools
for design entry, synthesis, simulation. Please visit Quick Log-
ic’s website at www.quicklogic.com for more information.
The variable grain logic cell features up to 17 simultaneous in-
puts and 6 outputs within a cell that can be fragmented into 6
independent sections. Each cell has a fan-in of 30 including
register and control lines (see Figure 5).
• 20 pre-defined Quad-clock networds, five per quadrant. Ac-
cessed by the 8 programmable global clock networks
• Sixteen high drive inputs. Two inputs located in each of the
eight I/O banks. Used as clock or enable signals for the I/O
RadHard flip-flops, or as high drive inputs for internal logic
Performance
• Input + logic cell + output total delays under 12ns
• Data path speeds over 200 MHz
• Counter speeds over 150 MHz
• FIFO speeds over 60+ MHz
WDATA
RAM
Module
(2,304 bits)
RDATA
WADDR
RADDR
RAM
Module
(2,304 bits)
WDATA
RDATA
Figure 3. RadHard Eclipse FPGA Module Bits
4
+
-
INPUT
REGISTER
Q
E
D
R
PAD
Q
OUTPUT
REGISTER
D
R
E
OUTPUT
ENABLE
REGISTER
D
Q
R
Figure 4. RadHard Eclipse FPGA I/O Cell
5
