UTRON
Rev. 1.1
FEATURES
Access time : 35/70ns (max.)
Low power consumption :
Operating : 45/30 mA (typ.)
CMOS Standby : 2mA (typ.) normal
2
µA
(typ.) L-version
1
µA
(typ.) LL-version
Single 4.5V~5.5V power supply
Operating temperature :
Commercial : 0℃~70℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
The UT6264C is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable input.(
CE
1
,CE2) ,and supports low
data retention voltage for battery back-up
operation with low data retention current.
The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully
TTL compatible.
PIN CONFIGURATION
NC
A12
A7
1
2
3
4
28
27
26
25
Vcc
WE
FUNCTIONAL BLOCK DIAGRAM
A0-A12
DECODER
8K
×
8
MEMORY
ARRAY
CE2
A8
A9
A11
OE
A6
A5
A4
UT6264C
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
Vcc
Vss
A3
A2
A1
A10
CE1
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
A0
I/O1
I/O2
I/O3
Vss
I/O8
I/O7
I/O6
I/O5
I/O4
CE1
CE2
OE
WE
CONTROL
CIRCUIT
PDIP/SOP
PIN DESCRIPTION
SYMBOL
A0 - A12
I/O1 - I/O8
CE1 ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No connection
GENERAL DESCRIPTION
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
1
UTRON
Rev. 1.1
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Commercial
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to +7.0
0 to +70
-65 to +150
1
50
260
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
CE
1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High - Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
ISB, ISB1
ISB, ISB1
Icc,Icc1,Icc2
Icc,Icc1,Icc2
Icc,Icc1,Icc2
note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V~5.5V, T
A
= 0℃ to 70℃)
SYMBOL TEST CONDITION
MIN. TYP. MAX.
Vcc
4.5
5.0
5.5
V
IH
2.2
-
V
CC
+0.5
V
IL
- 0.5
-
0.8
I
LI
-1
-
1
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC;
CE1 =V
IH;
or CE2=V
IL;
Output Leakage Current
I
LO
-1
-
1
or OE = V
IH
;
or
WE
= V
IL
Output High Voltage
V
OH
I
OH
= - 1mA
2.4
-
-
Output Low Voltage
V
OL
I
OL
= 4mA
-
-
0.4
- 35
-
45
60
Cycle time=Min,I
I/O
=
0mA;
I
CC
- 70
-
30
45
CE1 = V
IL ,
CE2= V
IH
Cycle time=1us; I
I/O
= 0mA
;
Operating Power
Icc1
-
20
30
CE1 =0.2V; CE2=Vcc-0.2V;
Supply Current
other pins at 0.2V or Vcc-0.2V
Cycle time=500ns;I
I/O
= 0mA;
-
10
15
Icc2
CE1 =0.2V; CE2=Vcc-0.2V;
other pins at 0.2V or Vcc-0.2V
Normal
-
1
10
CE1
= V
IH
or CE2= V
IL
I
SB
Standby Current (TTL)
- L/- LL
-
0.3
3
Normal
-
2
5
CE1
≧VCC-0.2V
;
-L
-
2
100
Standby Current (CMOS)
I
SB1
or CE2
≦
0.2V;
- LL
-
1
50
other pins at 0.2V or Vcc-0.2V
PARAMETER
Power Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
mA
mA
µA
µA
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
2
UTRON
Rev. 1.1
CAPACITANCE
(T
A
=25℃, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
-
-
MAX
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 100pF, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V~5.5V, T
A
= 0℃ to 70℃)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
SYMBOL
UT6264C-35
MIN.
MAX.
SYMBOL
UT6264C-35
MIN.
MAX.
UT6264C-70
MIN.
MAX.
UNIT
t
RC
t
AA
t
ACE1,
t
ACE2
t
OE
t
CLZ1*,
t
CLZ2*
t
OLZ*
t
CHZ1*,
t
CHZ2*
t
OHZ*
t
OH
35
-
-
-
10
5
-
-
5
-
35
35
25
-
-
25
25
-
70
-
-
-
10
5
-
-
5
-
70
70
35
-
-
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
UT6264C-70
MIN.
MAX.
UNIT
t
WC
t
AW
t
CW1,
t
CW2
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
35
30
30
0
25
0
20
0
5
-
-
-
-
-
-
-
-
-
-
15
70
60
60
0
50
0
30
0
5
-
-
-
-
-
-
-
-
-
-
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
3
UTRON
Rev. 1.1
TIMING WAVEFORMS
READ CYCLE
1 (Address Controlled)
(1,2,4)
t
RC
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE
1
, CE2 and
OE
Controlled)
(1,3,5,6)
t
RC
Address
CE1
t
ACE1
t
AA
CE2
t
ACE2
OE
t
CLZ1
t
CLZ2
Dout
HIGH-Z
t
OE
t
OLZ
t
OH
Data Valid
t
OHZ
t
CHZ1
t
CHZ2
HIGH-Z
Notes :
1.
WE
is HIGH for a read cycle.
2. Device is continuously selected
OE
,
CE
1
=V
IL
and CE2=V
IH.
3. Address must be valid prior to or coincident with
CE
1
4.
OE
is low.
low
and CE2 high transition; otherwise t
AA
is the limiting parameter.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with C
L
=5pF. Transition is measured
±
500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
4
UTRON
Rev. 1.1
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5,6)
t
Address
t
CE1
t
CE2
t
CW1
CW2
AW
WC
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
t
WE
AS
t
t
WHZ
t
WP
WR
t
High-Z
OW
Dout
Din
(4)
t
DW
t
Data Valid
(4)
DH
WRITE CYCLE 2
(
CE
1
and CE2 Controlled)
(1,2,5)
t
Address
WC
t
CE1
AW
t
AS
t
CW1
t
WR
t
CE2
CW2
WE
t
t
WHZ
WP
Dout
High-Z
t
Din
DW
t
Data Valid
DH
Notes :
1.
WE
or
CE
1
must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low
CE
1
, a high CE2 and a low
WE
.
3. During a
WE
controlled with write cycle with
OE
LOW, t
WP
must be greater than t
WHZ
+t
DW
to allow the I/O drivers to turn off
and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the
CE
1
LOW transition occurs simultaneously with or after
WE
LOW transition, the outputs remain in a high Impedance state.
6. t
OW
and t
WHZ
are specified with C
L
=5pF. Transition is measured
±
500mV from steady state.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
5
