Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable ( OE). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port.
R/ W
R
CE
R
OE
R
q
q
R/ W
L
CE
L
OE
L
A
11L
A
10L
I/O
8L
(7C139)
I/O
7L
I/O
0L
BUSY
L
A
9L
ROW
SELECT
MEMORY
ARRAY
ROW
SELECT
A
11R
A
10R
I/O
8R
(7C139)
COL
SEL
COLUMN
I/O
COLUMN
I/O
COL
SEL
I/O
7R
I/O
0R
BUSY
R
A
9R
A
0L
M/S
ARBITRATION
A
0R
Figure 1. Logic Block Diagram
NC
(2)
OE
R/W
L
I/O
1L
I/O
0L
A10
L
NC
A11
L
NC
CE
L
NC
NC
V
DD
A9
L
A8
L
63
A7
L
62
9
8
7
6
5
4
3
2
1
68
67
66
65
64
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
DD
GND
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
61
A6
L
60
59
58
57
56
55
54
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
NC
BUSY
L
GND
M/S
BUSY
R
NC
A
0R
A
1R
A
2R
A
3R
A
4R
7C138/139
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
R/W
R
I/O
7R
(1)
GND
Figure 2a. DPRAM Pinout (68-Flatpack)
(top view)
Notes:
1. I/O8R on the7C139
2. I/O8L on the 7C139
2
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
NC
A
11R
OE
R
CE
R
NC
NC
NC
NC
35
36
37
38
39
40
41
42
43
11
10
9
8
7
6
5
4
3
2
1
B11
A
5L
A10
B10
A
7L
A
6L
A9
B9
A
9L
A
8L
A8
B8
A
11L
A
10L
A7
B7
V
DD
NC
A6
B6
NC
NC
A5
B5
NC
CE
L
A4
B4
OE
L
R/W
L
A3
B3
I/O
0L
NC
(2)
A2
B2
I/O
1L
I/O
2L
B1
I/O
3L
C11
A
4L
C10
A
3L
D11
A
2L
D10
A
1L
E11
A
0L
E10
NC
F11
BUSY
L
F10
GND
G11
M/S
G10
BUSY
R
7C138/139
C2
I/O
4L
C1
I/O
5L
D2
GND
D1
I/O
6L
E2
I/O
7L
E1
V
DD
F2
GND
F1
I/O
0R
G2
I/O
1R
G1
I/O
2R
K11
A
3R
K10
A
4R
K9
A
7R
K8
A
9R
K7
A
11R
K6
GND
K5
NC
K4
NC
K3
OE
R
H2
J2
K2
V
DD
I/O
4R
I/O
7R
H1
J1
K1
I/O
3R
I/O
5R
I/O
6R
H11
NC
H10
A
0R
J11
A
1R
J10
A
2R
L10
A
5R
L9
A
6R
L8
A
8R
L7
A
10R
L6
NC
L5
NC
L4
CE
R
L3
R/W
R
L2
NC
(1)
A
Notes:
1. I/O8R on the7C139
2. I/O8L on the 7C139
B
C
D
E
F
G
H
J
K
L
Figure 2b: DPRAM Pinout (68 PGA)
(top view)
PIN NAMES
LEFT PORT
I/O
0L-7L(8L)
A
0L-11L
CE
L
OE
L
R/W
L
BUSY
L
M/S
V
DD
GND
RIGHT PORT
I/O
0R-7R(8R)
A
0R-11R
CE
R
OE
R
R/W
R
BUSY
R
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Busy Flag Input/Output
Master or Slave Select
Power
Ground
DESCRIPTION
3
The UT7C138/139 consists of an array of 4K words of 8 or 9
bits of dual-port SRAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. With the M/S pin, the UT7C138/139 can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). Each port is provided with its own
output enable control (OE), which allows data to be read from
the device.
WRITE CYCLE
A combination of R/W less than V
IL
(max), and CE less than
V
IL
(max), defines a write cycle. The state of OE is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when either OE is greater than V
IH
(min), or
when R/W is less than V
IL
(max).
WRITE OPERATION
Write Cycle 1, the Write Enable-controlled Access shown in
figure 4a, is defined by a write terminated by R/W going high
with CE active. The write pulse width is defined by t
PWE
when
the write is initiated by R/W, and by t
SCE
when the write is
initiated by CE going active. Unless the outputs have been
previously placed in the high-impedance state by OE, the user
must wait t
HZOE
before applying data to the eight/nine
bidirectional pins I/O(0:7/0:8) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in
figure 4b, is defined by a write terminated byCE going inactive.
The write pulse width is defined by t
PWE
when the write is
initiated by R/W, and by t
SCE
when the write is initiated by CE
going active. For the R/W initiated write, unless the outputs have
been previously placed in the high-impedance state by OE, the
user must wait t
HZWE
before applying data to the eight/nine
bidirectional pins I/O(0:7/0:8) to avoid bus contention.
If a location is being written by one port and the opposite port
attempts to read that location, a port-to-port flow through delay
must be met before the data is read on the output. Data will be
valid on the port wishing to read the location (t
BZA
+ t
BDD
) after
the data is written on the other port (see figure 5a).
READ OPERATION
When reading the device, the user must assert both the OE and
CE pins. Data will be available t
ACE
after CE or t
DOE
after OE
is asserted (see figures 3a and 3b).
MASTER/SLAVE
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
Writing of slave devices must be delayed until after the BUSY
input has settled. Otherwise, the slave chip may begin a write
cycle during a contention situation. When presented as a HIGH
input, the M/S pin allows the device to be used as a master and,
therefore, the BUSY line is an output. BUSY can then be used
to send the arbitration outcome to a slave. When presented as a
LOW input, the M/S pin allows the device to be used as a slave,
and, therefore, the BUSY pin is an input.
Table 1. Non-Contending Read/Write
INPUTS
CE
H
X
L
L
L
R/W
X
X
H
L
X
OE
X
H
L
X
X
OUTPUTS
I/O
0-7
High Z
High Z
Data Out
Data In
---
OPERATION
Power Down
I/O Lines
Disabled
Read
Write
Illegal
Condition
RADIATION HARDNESS
The UT7C138/139 incorporates special design and layout
features which allow operation in high-level radiation
environments. UTMC has developed special low-temperature
processing techniques designed to enhance the total-dose
radiation hardness of both the gate oxide and the field oxide
while maintaining the circuit density and reliability. For
transient radiation hardness and latchup immunity, UTMC
builds all radiation-hardened products on epitaxial wafers using
an advanced twin-tub CMOS process. In addition, UTMC pays
special attention to power and ground distribution during the
design phase, minimizing dose-rate upset caused by rail
collapse.
Table 2. Radiation Hardness
Design Specifications
1
Total Dose
LET Threshold
Neutron Fluence
2
Memory Device
Cross Section @ LET
= 120MeV-cm
2
/mg
1.0E6
85
3.0E14
< 1.376E
-2
(4Kx8)
< 1.548E
-2
(4Kx9)
rads(Si)
MeV-cm
2
/mg
n/cm
2
cm
2
Notes:
1. The DPRAM will not latchup during radiation exposure under recommended
operating conditions.
2. Not tested for CMOS technology.
4
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.5 to 7.0V
-0.5 to (V
DD
+ 0.3)V
-65 to +150°C
2.0W
+150°C
3.3°C/W
±
10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012, infinite heat sink.
