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UZNBG4001Q16

Analog Circuit, 1 Func, PDSO16, QSOP-16

器件类别:模拟混合信号IC    信号电路   

厂商名称:Diodes Incorporated

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器件参数
参数名称
属性值
零件包装代码
SOIC
包装说明
SSOP,
针数
16
Reach Compliance Code
unknown
模拟集成电路 - 其他类型
ANALOG CIRCUIT
JESD-30 代码
R-PDSO-G16
JESD-609代码
e3
长度
4.85 mm
湿度敏感等级
1
功能数量
1
端子数量
16
最高工作温度
70 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
SSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度)
260
认证状态
Not Qualified
座面最大高度
1.75 mm
最大供电电压 (Vsup)
12 V
最小供电电压 (Vsup)
5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
温度等级
OTHER
端子面层
MATTE TIN
端子形式
GULL WING
端子节距
0.635 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
40
宽度
3.9 mm
Base Number Matches
1
文档预览
FET BIAS CONTROLLER
ISSUE 2 - JUNE 1998
DEVICE DESCRIPTION
The ZNBG series of devices are designed to
meet the bias requirements of GaAs and
HEMT FETs commonly used in satellite
receiver LNBs, PMR, cellular telephones etc.
with a minimum of external components.
With the addition of two capacitors and
resistors the devices provide drain voltage
and current control for a number of external
grounded source FETs, generating the
regulated negative rail required for FET gate
biasing whilst operating from a single
supply. This negative bias, at -3 volts, can
also be used to supply other external
circuits.
The ZNBG4000/1 and ZNBG6000/1 contain
four and six bias stages respectively. In
setting drain current the ZNBG4000/1 two
resistors allows individual FET pair control
to different levels, the ZNBG6000/1 two
resistors split control between two and four
FETs. This allows the operating current of
input FETs to be adjusted to minimise noise,
whilst the following FET stages can
separately be adjusted for maximum gain.
The series also offers the choice of drain
v ol t a ge t o b e s e t f or t he F E T s , the
ZNBG4000/6000 gives 2.2 volts drain whilst
the ZNBG4001/6001 gives 2 volts.
ZNBG4000 ZNBG4001
ZNBG6000 ZNBG6001
These devices are unconditionally stable
over the full working temperature with the
FETs in place, subject to the inclusion of the
recommended gate and drain capacitors.
These ensure RF stability and minimal
injected noise.
It is possible to use less than the devices full
complement of FET bias controls, unused
drain and gate connections can be left open
circuit without affecting operation of the
remaining bias circuits.
In order to protect the external FETs the
circuits have been designed to ensure that,
under any conditions including power
up/down transients, the gate drive from the
bias circuits cannot exceed the range -3.5V
to 0.7V. Furthermore if the negative rail
experiences a fault condition, such as
overload or short circuit, the drain supply to
the FETs will shut down avoiding excessive
current flow.
The ZNBG4000/1 and ZNBG6000/1 are
available in QSOP16 and 20 pin packages
respectively for the minimum in devices size.
Device operating temperature is -40 to 70°C
to suit a wide range of environmental
conditions.
FEATURES
APPLICATIONS
Provides bias for GaAs and HEMT FETs
Drives up to four or six FETs
Dynamic FET protection
Drain current set by external resistor
Regulated negative rail generator
requires only 2 external capacitors
Choice in drain voltage
Wide supply voltage range
QSOP surface mount package
Satellite receiver LNBs
Private mobile radio (PMR)
Cellular telephones
4-137
ZNBG4000 ZNBG4001
ZNBG6000 ZNBG6001
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Supply Current
Drain Current (per FET)
(set by R
CAL1
and R
CAL2
)
Output Current
Operating Temperature
Storage Temperature
-0.6V to 15V
100mA
0 to 15mA
100mA
-40 to 70°C
-50 to 85°C
Power Dissipation (T
amb
=
25°C)
QSOP16
500mW
QSOP20
650mW
ELECTRICAL CHARACTERISTICS TEST CONDITIONS (Unless otherwise stated):
T
amb
=
25°C,V
CC
=5V,I
D
=10mA (R
CAL1
=33kΩ;R
CAL2
=33kΩ)
SYMBOL PARAMETER
CONDITIONS
Min
V
CC
I
CC
I
CC
V
SUB
Supply Voltage
Supply Current
ZNBG4000/1
Supply Current
ZNBG6000/1
Substrate Voltage
(Internally generated)
Output Noise
Drain Voltage
Gate Voltage
Oscillator Freq.
Current
Current Change
∆I
DV
∆I
DT
V
D
with V
CC
with T
j
Voltage
ZNBG4000, ZNGB6000
ZNBG4001, ZNBG6001
Voltage Change
V
DV
V
DT
with V
CC
with T
j
V
CC
= 5 to 12V
T
j
= -40 to +70°C
0.5
50
%/V
ppm
V
CC
=5 to 12V
T
j
=-40 to +70°C
2
1.8
0.02
0.05
2.2
2
2.4
2.2
%/V
%/°C
V
V
I
D1
to I
D4
=0
I
D1
to I
D4
=10mA
ID1 to I
D6
=0
I
D1
to I
D6
=10mA
I
SUB
= 0
I
SUB
= -200µA
C
G
=4.7nF, C
D
=10nF
C
G
=4.7nF, C
D
=10nF
200
8
350
10
-3.5
-3
5
LIMITS
Typ
Max
12
10
50
15
75
-2
-2
0.02
0.005
800
12
V
mA
mA
mA
mA
V
V
Vpkpk
Vpkpk
kHz
mA
UNITS
E
ND
E
NG
f
O
I
D
DRAIN CHARACTERISTICS
4-138
ZNBG4000 ZNBG4001
ZNBG6000 ZNBG6001
SYMBOL PARAMETER
CONDITIONS
Min
LIMITS
Typ
Max
2000
µA
UNITS
GATE CHARACTERISTICS
I
GO
Output Current Range
Output Voltage
ZNBG4000/1
V
OL
Output Low
I
D1
to I
D4
=12mA
I
G1
to I
G4
=0
I
D1
to I
D4
=12mA
I
G1
to I
G4
= -10µA
V
OH
Output High
Output Voltage
ZNBG6000/1
V
OL
Output Low
I
D1
to I
D6
=12mA
I
G1
to I
G6
= 0
I
D1
to I
D6
=12mA
I
G1
to I
G6
= -10µA
V
OH
Notes:
1. The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, C
NB
and C
SUB
, of
47nF are required for this purpose.
2. The characteristics are measured using two external reference resistors R
CAL1
and R
CAL2
of value 33kΩ wired from pins R
CAL1/2
to
ground. For the ZNBG4000, resistor R
CAL1
sets the drain current of FETs 1 and 2, resistor R
CAL2
sets the drain current of FETs 3 and 4.
For the ZNBG6000, resistor R
CAL1
sets the drain current of FETs 1 and 4, resistor R
CAL2
sets the drain current of FETs 2, 3, 5 and 6.
-30
-3.5
-3.5
0
-2
-2
1
V
V
V
I
D1
to I
D4
= 8mA
I
G1
to I
G4
= 0
-3.5
-3.5
0
-2
-2
1
V
V
V
Output High
I
D1
to I
D6
= 8mA
I
G1
to I
G6
= 0
3. Noise voltage is not measured in production.
4. Noise voltage measurement is made with FETs and gate and drain capacitors in place on all
outputs. C
G
, 4.7nF, are connected between gate outputs and ground, C
D
, 10nF, are connected
between drain outputs and ground.
4-139
ZNBG4000 ZNBG4001
ZNBG6000 ZNBG6001
TYPICAL CHARACTERISTICS
16
Vcc = 5V
14
12
10
8
6
4
2
0
0
20
40
60
80
100
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
Note:- Operation with loads > 200µA
is not guaranteed.
Vcc = 5V
6V
8V
10V
0
0.2
0.4
0.6
0.8
1.0
R
cal
(k)
External Vsub Load (mA)
JFET Drain Current v R
cal
V
sub
v External Load
2.4
2.3
2.2
Vcc = 5V
6V
8V
10V
2.1
2.0
2
4
6
8
10
12
14
16
Drain Current (mA)
JFET Drain Voltage v Drain Current
4-140
ZNBG4000 ZNBG4001
ZNBG6000 ZNBG6001
FUNCTIONAL DIAGRAM
FUNCTIONAL DESCRIPTION
The ZNBG devices provide all the bias requirements for external FETs, including the generation
of the negative supply required for gate biasing, from the single supply voltage.
The diagram above shows a single stage from the ZNBG series. The ZNBG4000/1 contains 4 such
stages, the ZNBG6000/1 contains 6. The negative rail generator is common to all devices.
The drain voltage of the external FET Q
N
is set by the ZNBG device to its normal operating voltage.
This is determined by the on board V
D
Set reference, for the ZNBG4000/6000 this is nominally
2.2 volts whilst the ZNBG4001/6001 provides nominally 2 volts.
The drain current taken by the FET is monitored by the low value resistor I
D
Sense. The amplifier
driving the gate of the FET adjusts the gate voltage of Q
N
so that the drain current taken matches
the current called for by an external resistor R
CAL
. Both ZNBG devices have the facility to program
different drain currents into selected FETs. Two R
CAL
inputs are provided. For the ZNBG4000,
resistor R
CAL1
sets the drain current of FETs 1 and 2, resistor R
CAL2
sets the drain current of FETs
3 and 4. For the ZNBG6000, resistor R
CAL1
sets the drain current of FETs 1 and 4, resistor R
CAL2
sets the drain current of FETs 2, 3, 5 and 6.
Since the FET is a depletion mode transistor, it is usually necessary to drive its gate negative with
respect to ground to obtain the required drain current. To provide this capability powered from
a single positive supply, the device includes a low current negative supply generator. This
generator uses an internal oscillator and two external capacitors, C
NB
and C
SUB
.
4-141
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参数对比
与UZNBG4001Q16相近的元器件有:UZNBG6000Q20、UZNBG4000Q16、UZNBG6001Q20。描述及对比如下:
型号 UZNBG4001Q16 UZNBG6000Q20 UZNBG4000Q16 UZNBG6001Q20
描述 Analog Circuit, 1 Func, PDSO16, QSOP-16 Analog Circuit, 1 Func, PDSO20, QSOP-20 Analog Circuit, 1 Func, PDSO16, QSOP-16 Analog Circuit, 1 Func, PDSO20, QSOP-20
零件包装代码 SOIC QSOP SOIC QSOP
包装说明 SSOP, SSOP, SSOP, SSOP,
针数 16 20 16 20
Reach Compliance Code unknown unknown unknown unknow
模拟集成电路 - 其他类型 ANALOG CIRCUIT ANALOG CIRCUIT ANALOG CIRCUIT ANALOG CIRCUIT
JESD-30 代码 R-PDSO-G16 R-PDSO-G20 R-PDSO-G16 R-PDSO-G20
JESD-609代码 e3 e3 e3 e3
长度 4.85 mm 8.645 mm 4.85 mm 8.645 mm
湿度敏感等级 1 1 1 1
功能数量 1 1 1 1
端子数量 16 20 16 20
最高工作温度 70 °C 70 °C 70 °C 70 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SSOP SSOP SSOP SSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度) 260 260 260 260
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.75 mm 1.75 mm 1.75 mm 1.75 mm
最大供电电压 (Vsup) 12 V 12 V 12 V 12 V
最小供电电压 (Vsup) 5 V 5 V 5 V 5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V
表面贴装 YES YES YES YES
温度等级 OTHER OTHER OTHER OTHER
端子面层 MATTE TIN MATTE TIN MATTE TIN MATTE TIN
端子形式 GULL WING GULL WING GULL WING GULL WING
端子节距 0.635 mm 0.635 mm 0.635 mm 0.635 mm
端子位置 DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 40 40 40 40
宽度 3.9 mm 3.9 mm 3.9 mm 3.9 mm
厂商名称 - Diodes Incorporated Diodes Incorporated Diodes Incorporated
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