R
EM MICROELECTRONIC -
MARIN SA
V3021
Ultra Low Power 1-Bit 32 kHz RTC
Description
The V3021 is a low power CMOS real time clock. Data is
transmitted serially as 4 address bits and 8 data bits, over
one line of a standard parallel data bus. The device is
accessed by chip select (
CS ) with read and write control
timing provided by either
RD
and
WR
pulse (Intel CPU)
or DS with advanced R/
W
(Motorola CPU). Data can
also be transmitted over a conventional 3 wire serial
interface having CLK, data I/O and strobe. The V3021
has no busy states and there is no danger of a clock
update while accessing.
Supply current is typically
800 nA at V
DD
= 3.0V. Battery operation is supported by
complete functionality down to 2.0V. The oscillator is
typically 0.3 ppm/V.
Features
Supply current typically 800 nA at 3V
50 ns access time with 50 pF load capacitance
Fully operational from 2.0V to 5.5V
No busy states or danger of a clock update while
accessing
Serial communication on one line of a standard
parallel data bus or over a conventional 3 wire serial
interface
Interface compatible with both Intel and Motorola
Seconds, minutes, hours, day of month, month, year,
week day and week number in BCD format
Leap year and week number correction
Time set lock mode to prevent unauthorized setting of
the current time or date
Oscillator stability 0.3 ppm / volt
No external capacitor needed
Frequency measurement and test modes
Temperature range: -40°C to +85°C
On request extended temperature range, -40°C to
+125°C
Packages DIP8 and SO8
Applications
Utility meters
Battery operated and portable equipment
Consumer electronics
White/brown goods
Pay phones
Cash registers
Personal computers
Programmable controller systems
Data loggers
Automotive systems
Typical Operating Configuration
or R/
Pin Assignment
or
CPU
SO8
XI
XO
Address
Decoder
V
DD
WR
V3021
CS
RD
CS
V
SS
XI
V3021
XO
I/O
Address Bus
RD
WR
I/O
Data Bus
Fig. 2
CS
RD
WR
RAM
Fig. 1
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V3021
Absolute Maximum Ratings
Parameter
Maximum voltage at V
DD
Minimun voltage at V
DD
Maximum voltage at any
signal pin
Minimum voltage at any signal
pin
Maximum storage
temperature
Minimum storage temperature
Electrostatic discharge
maximum to MIL-STD-883C
method 3015.7 with ref. to V
SS
Maximum soldering conditions
Symbol
V
DDmax
V
DDmin
V
max
V
min
T
STOmax
T
STOmin
V
Smax
T
Smax
Handling Procedures
Conditions
V
SS
+ 7.0V
V
SS
– 0.3V
V
DD
+ 0.3V
V
SS
– 0.3V
+150°C
-65°C
1000V
250°C x 10s
Table 1
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when
all terminal voltages are kept within the voltage range.
Unused inputs must always be tied to a defined logic
voltage level.
Operating Conditions
Parameter
Symbol
Operating temperature
T
A
Logic supply voltage
V
DD
Supply voltage dv/dt
(power-up & power-down)
Decoupling capacitor
Crystal Characteristics
1)
Frequency
f
Load capacitance
C
L
Series resistance
R
S
1)
Min
-40
2.0
Typ
5.0
Max Unit
+125 °C
5.5
V
6
V/µs
nF
kHz
pF
100
32.768
8.2
35
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability
or cause malfunction.
7
12.5
50
kΩ
Table 2
See Fig. 3
Electrical Characteristics (standard temperature range)
V
DD
= 5.0V ±10%, V
SS
= 0V and T
A
=-40 to +85°C, unless otherwise specified
Parameter
Symbol
Test Conditions
Total static supply
I
SS
All outputs open, all inputs at V
DD
V
DD
= 3.0V, address 0 = 0
Total static supply
I
SS
All outputs open, all inputs at V
DD
V
DD
= 5V, address 0 = 0
T
A
= +25°C
Dynamic current
I
SS
I/O to V
SS
through 1M
Ω
RD
= V
SS
,
WR
= V
DD
,
CS = 4 MHz
address 0 = 0, read all 0
Input / Output
Input logic low
V
IL
Input logic high
V
IH
Output logic low
V
OL
I
OL
= 4 mA
Output logic high
V
OH
I
OH
= 4 mA
Input leakage
I
IN
0.0 < V
IN
< 5.0V
Output tri-state leakage on I/O
I
TS
CS high, and address 0, bit 0, low
pin
Oscillator
Starting voltage
V
STA
Input capacitance on XI
C
IN
T
A
= +25°C
Output capacitance on XO
C
OUT
T
A
= +25°C
Start-up time
T
STA
1.5
≤
V
DD
≤
5.5V, T
A
= +25°C
Frequency stability
∆
f/f
Frequency Measurement Mode
Current source on I/O pin
I
ONF
CS high, addr.0, bit 0, high
pulsed on/off @ 256 Hz
V
I/O
= 1V
Min
Typ
0.8
1.3
Max
1.8
10
3
300
Unit
µA
µA
µA
µA
1.0
3.5
0.4
2.4
0.1
0.1
1.8
13
9
1
0.3
10
25
1
1
V
V
V
V
µA
µA
V
pF
pF
s
ppm/V
µA
Table 3
0.5
60
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V3021
Electrical Characteristics (extended temperature range)
V
DD
= 5.0V ±10%, V
SS
= 0V and T
A
=-40 to +125°C, unless otherwise specified
Parameter
Symbol
Test Conditions
Total static supply
I
SS
All outputs open, all inputs at V
DD
V
DD
= 3.0V, address 0 = 0
Total static supply
I
SS
All outputs open, all inputs at V
DD
address 0 = 0
Dynamic current
I
SS
I/O to V
SS
through 1M
Ω
RD
= V
SS
,
WR
= V
DD
,
CS = 4 MHz
address 0 = 0, read all 0
Input / Output
Input logic low
V
IL
Input logic high
V
IH
Output logic low
V
OL
I
OL
= 4 mA
Output logic high
V
OH
I
OH
= 4 mA
Input leakage
I
IN
0.0 < V
IN
< 5.0V
Output tri-state leakage on I/O
I
TS
CS high, and address 0, bit 0, low
pin
Oscillator
Starting voltage
V
STA
Supply voltage dV/dt (power-
+85°C
≤
T
A
≤
+125°C
up & power-down)
Input capacitance on XI
C
IN
T
A
= +25°C
Output capacitance on XO
C
OUT
T
A
= +25°C
Series resistance of the
R
S
-40°C
≤
T
A
≤
+85°C
crystal
Start-up time
T
STA
T
A
= +125°C (note 1)
2.0
≤
V
DD
≤
5.5V, T
A
= +25°C
Frequency stability
∆
f/f
Frequency Measurement Mode
Current source on I/O pin
I
ONF
CS high, addr.0, bit 0, high
pulsed on/off @ 256 Hz
V
I/O
= 1V
Min
Typ
Max
4.9
8.3
300
Unit
µA
µA
µA
1.0
3.5
0.4
2.4
0.1
0.1
2.0
0.006
13
9
90
10
0.3
8
25
0.5
60
1
1
V
V
V
V
µA
µA
V
V/µs
pF
pF
k
Ω
s
ppm/V
µA
Table 3 ex
6
Note 1
: Analyses done at high temperature with crystal type Micro Crystal CX2V-02
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V3021
The V3021 will run slightly too fast, in order to allow the
user to adjust the frequency, depending on the mean
operating temperature. This is made since the crystal
adjustment can only work by lowering the frequency with
an added capacitor between XO and V
SS
. The printed
circuit capacitance has also to be taken into
consideration. The V3021 in DIL 8 package, running with
an 8.2 pF crystal at room temperature, will be adjusted to
better than ±1s/day with a 6.8 pF capacitor.
Typical Frequency on I/O Pin
Typical drift for ideal 32'768 Hz quartz
Note
: The trimming capacitor value must not exceed
15 pF. Greater values may disturb the oscillator
function
Fig. 3
Quartz Characteristics
∆
F
ppm
2
= -0.038
(T – T
O
) ± 10%
F
O
°
C
2
∆F/F
O
=
the ratio of the change in frequency to the
nominal value expressed in ppm (it can be
thought of as the frequency deviation at any
temperature)
the temperature of interest in °C
the turnover temperature (25 ± 5°C)
T
T
O
=
=
To determine the clock error (accuracy) at a given
temperature, add the frequency tolerance at 25°C to the
value obtained from the formula above.
Fig. 4
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V3021
Timing Characteristics (standard temperature range)
V
SS
= 0V and T
A
=-40 to +85°C, unless otherwise specified
Parameter
Symbol Test Conditions
Chip select duration
RAM access time
(note 1)
Time between two transfers
Rise time
(note 2)
Fall time
(note 2)
Data valid to Hi-impedance
(note 3)
Write data settle time
(note 4)
Data hold time
(note 5)
Advance write time
Write pulse time
(note 6)
t
CS
t
ACC
t
W
t
R
t
F
t
DF
t
DW
t
DH
t
ADW
t
WC
Write cycle
C
LOAD
= 50pF
500
10
10
10
60
80
25
200
200
200
100
Min. Max.
V
DD
≥
2V
200
180
Min.
Typ.
Max.
V
DD
= 5.0V ±10%
50
50
100
10
10
15
50
25
10
50
30
200
200
40
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4
Timing Characteristics (standard temperature range)
V
SS
= 0V and T
A
=-40 to +125°C, unless otherwise specified
Parameter
Symbol Test Conditions
Chip select duration
RAM access time
(note 1)
Time between two transfers
Rise time
(note 2)
Fall time
(note 2)
Data valid to Hi-impedance
(note 3)
Write data settle time
(note 4)
Data hold time
(note 5)
Advance write time
Write pulse time
(note 6)
t
CS
t
ACC
t
W
t
R
t
F
t
DF
t
DW
t
DH
t
ADW
t
WC
Write cycle
C
LOAD
= 50pF
500
10
10
10
60
80
25
200
100
100
100
Min. Max.
V
DD
≥
2V
200
180
Min.
Typ.
Max.
V
DD
= 5.0V ±10%
60
50
120
10
10
5
50
25
15
60
30
100
100
50
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4 ex.
Note 1
: t
ACC
starts from
RD
or CS , whichever activates last
Typically, t
ACC
= 5 + 0.9 C
EXT
in ns; where C
EXT
(external parasitic capacitance) is in pF
Note 2
: CS ,
RD
, DS ,
WR
and R/
W
rise and fall times are specified by t
R
and t
F
Note 3
: t
DF
starts from
RD
or CS , whichever deactivates first
Note 4
: t
DW
ends at
WR
or CS , whichever deactivates first
Note 5
: t
DH
starts from
WR
or CS , whichever deactivates first
Note 6
: t
WC
starts from
WR
or CS , whichever activates last and ends at
WR
or CS , whichever deactivates first
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