V54C3256(16/80/40)4V(T/S/B)
256Mbit SDRAM
3.3 VOLT, TSOP II / SOC / WBGA PACKAGE
16M X 16, 32M X 8, 64M X 4
PRELIMINARY
CILETIV LESO M
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
Features
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■
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4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
4 banks x16Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II, 60 Ball WBGA and
SOC
LVTTL Interface
Single +3.3 V
±0.3
V Power Supply
Description
The V54C3256(16/80/40)4V(T/S/B) is a four
bank Synchronous DRAM organized as 4 banks x
4Mbit x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit
x 4. The V54C3256(16/80/40)4V(T/S/B) achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
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Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T/S/B
•
Access Time (ns)
6
•
Power
8PC
•
7PC
•
7
•
Std.
•
L
•
Temperature
Mark
Blank
V54C3256(16/80/40)4V(T/S/B) Rev. 1.4 April 2002
1
V54C3256(16/80/40)4V(T/S/B)
CILETIV LESO M
256Mbit SDRAM Part Numbers
Part Number
V54C3256164VAT
V54C3256804VAT
V54C3256404VAT
V54C3256164VBT
V54C3256804VBT
V54C3256404VBT
V54C3256164VAB
V54C3256804VAB
V54C3256404VAB
V54C3256164VBS
V54C3256804VBS
V54C3256404VBS
Configuration
16M x 16
32M x 8
64M x 4
16M x 16
32M x 8
64M x 4
16M x 16
32M x 8
64M x 4
16M x 16
32M x 8
64M x 4
Process
0.17um
0.17um
0.17um
0.14um
0.14um
0.14um
0.17um
0.17um
0.17um
0.14um
0.14um
0.14um
Package
TSOP
TSOP
TSOP
TSOP
TSOP
TSOP
WBGA
WBGA
WBGA
SOC
SOC
SOC
V54C3256(16/80/40)4V(T/S/B) Rev. 1.4 April 2002
2
V54C3256(16/80/40)4V(T/S/B)
CILETIV LESOM
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
V 54 C 3 25616 4 V A L T
Device
Number
Special
Feature
Speed
6 ns
7 ns
8 ns
TSOP Component
Package
L=Low Power
4 Banks
Component Rev Level A=0.17um
B=0.14um
V=LVTTL
Description
TSOP-II
Pkg.
T
Pin Count
54
C=CMOS Family
3.3V, LVTTL INTERFACE
16Mx16(8K Refresh)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
V
CC
I/O
1
V
CCQ
I/O
2
I/O
3
V
SSQ
I/O
4
I/O
5
V
CCQ
I/O
6
I/O
7
V
SSQ
I/O
8
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356164V-01
Pin Names
CLK
CKE
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V
SS
I/O
16
V
SSQ
I/O
15
I/O
14
V
CCQ
I/O
13
I/O
12
V
SSQ
I/O
11
I/O
10
V
CCQ
I/O
9
V
SS
NC
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
CS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
16
LDQM, UDQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80/40)4V(T/S/B) Rev. 1.4 April 2002
3
V54C3256(16/80/40)4V(T/S/B)
CILETIV LESO M
V 54 C 3 25680 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
C=CMOS Family
Device
Number
Special
Feature
Speed
6 ns
7 ns
8 ns
TSOP Component
Package
L=Low Power
4 Banks
Component Rev Level A=0.17um
B=0.14um
V=LVTTL
Description
TSOP-II
Pkg.
T
Pin Count
54
3.3V, LVTTL INTERFACE
32Mx8(8K Refresh)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
CKE
CS
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V
CC
I/O
1
V
CCQ
NC
I/O
2
V
SSQ
NC
I/O
3
V
CCQ
NC
I/O
4
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356804V-01
V
SS
I/O
8
V
SSQ
NC
I/O
7
V
CCQ
NC
I/O
6
V
SSQ
NC
I/O
5
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
8
DQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80/40)4V(T/S/B) Rev. 1.4 April 2002
4
V54C3256(16/80/40)4V(T/S/B)
CILETIV LESOM
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
V 54 C 3 25640 4 V A L T
Device
Number
Special
Feature
Speed
6 ns
7 ns
8 ns
TSOP Component
Package
L=Low Power
4 Banks
Component Rev Level A=0.17um
B=0.14um
V=LVTTL
Description
TSOP-II
Pkg.
T
Pin Count
54
C=CMOS Family
3.3V, LVTTL INTERFACE
64Mx4(8K Refresh)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
CLK
CKE
CS
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V
CC
NC
V
CCQ
NC
I/O
1
V
SSQ
NC
NC
V
CCQ
NC
I/O
2
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356404V-01
V
SS
NC
V
SSQ
NC
I/O
4
V
CCQ
NC
NC
V
SSQ
NC
I/O
3
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
4
DQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80/40)4V(T/S/B) Rev. 1.4 April 2002
5
