V54C3256(16/80/40)4VD
256Mbit SDRAM
(3.0~3.3) VOLT, TSOP II / FBGA PACKAGE
16M X 16, 32M X 8, 64M X 4
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
Features
■
■
■
■
■
■
■
■
■
■
■
4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
4 banks x16Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II, 60 Ball FBGA, 54
Ball FBGA
LVTTL Interface
Single (+3.0V~3.3 V)
±0.3
V Power Supply
Description
The V54C3256(16/80/40)4VD is a four bank Syn-
chronous DRAM organized as 4 banks x 4Mbit x 16,
4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4. The
V54C3256(16/80/40)4VD achieves high speed data
transfer rates up to 166 MHz by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
■
■
■
■
■
■
■
■
■
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
T/S
•
Access Time (ns)
6
•
Power
7
•
7PC
•
Std.
•
L
•
U
•
Temperature
Mark
Blank
V54C3256(16/80/40)4VD Rev. 1.9 August 2008
1
ProMOS TECHNOLOGIES
Part Number Information
V54C3256(16/80/40)4VD
V
ProMOS
5 4
C
3
2 5 6 8 0
ORGANIZATION
& REFRESH
1Mx16, 2K : 1616
4Mx16, 4K : 6516
4
V
D
T
7 5
PC
OTHER
PC
: CL2
TYPE
54 : SDRAM
55 : MOBILE SDRAM
32Mx4, 4K : 12840
16Mx8, 4K : 12880
64Mx4, 8K : 25640
32Mx8, 8K : 25680
128Mx4, 8K : 51240
64Mx8, 8K : 51280
8Mx16, 4K : 12816
BLANK: CL3
TEMPERATURE
BLANK: 0 - 70C
16Mx16, 8K : 25616
32Mx16, 8K : 51216
I:
H:
E:
-40 - 85C
-40 - 105C
-40 - 125C
7 : 143MHz
6 : 166MHz
5 : 200MHz
CMOS
BANKS
VOLTAGE
2 : 2 BANKS
4 : 4 BANKS
8 : 8 BANKS
REV LEVEL
A: 1st
B: 2nd
C: 3rd
D: 4th
PACKAGE
LEAD
PLATING
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
T
S
C
B
D
Z
R
E
F
G
H
RoHS
I/O
V: LVTTL
SPEED
10 : 100MHz
8 : 125MHz
75 : 133MHz
4:
3:
2:
1:
3.0V
3.0V ~3.3 V
2.5 V
1.8 V
GREEN PACKAGE
DESCRIPTION
I
J
K
M
N
P
TSOP
60-Ball FBGA
54-BallFBGA
BGA
Die-stacked TSOP
Die-stacked FBGA
* RoHS: Restriction of Hazardous Substances
* Green: RoHS-compliant and Halogen-free
V54C3256(16/80/40)4VD Rev. 1.9 August 2008
2
ProMOS TECHNOLOGIES
V54C3256(16/80/40)4VD
Description
TSOP-II
Pkg.
T
Pin Count
54
54 Pin Plastic TSOP-II
x16 PIN CONFIGURATION
Top View
V
CC
I/O
1
V
CCQ
I/O
2
I/O
3
V
SSQ
I/O
4
I/O
5
V
CCQ
I/O
6
I/O
7
V
SSQ
I/O
8
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356164V-01
Pin Names
CLK
CKE
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.0V~3.3V)
Ground
Power for I/O’s (+3.0V~3.3V)
Ground for I/O’s
Not connected
V
SS
I/O
16
V
SSQ
I/O
15
I/O
14
V
CCQ
I/O
13
I/O
12
V
SSQ
I/O
11
I/O
10
V
CCQ
I/O
9
V
SS
NC
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
CS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
16
LDQM, UDQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80/40)4VD Rev. 1.9 August 2008
3
ProMOS TECHNOLOGIES
V54C3256(16/80/40)4VD
Description
TSOP-II
Pkg.
T
Pin Count
54
54 Pin Plastic TSOP-II
x8 PIN CONFIGURATION
Top View
Pin Names
CLK
CKE
CS
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.0V~3.3V)
Ground
Power for I/O’s (+3.0V~3.3V)
Ground for I/O’s
Not connected
V
CC
I/O
1
V
CCQ
NC
I/O
2
V
SSQ
NC
I/O
3
V
CCQ
NC
I/O
4
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356804V-01
V
SS
I/O
8
V
SSQ
NC
I/O
7
V
CCQ
NC
I/O
6
V
SSQ
NC
I/O
5
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
8
DQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80/40)4VD Rev. 1.9 August 2008
4
ProMOS TECHNOLOGIES
V54C3256(16/80/40)4VD
Description
TSOP-II
Pkg.
T
Pin Count
54
54 Pin Plastic TSOP-II
x4 PIN CONFIGURATION
Top View
Pin Names
CLK
CKE
CS
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.0V~3.3V)
Ground
Power for I/O’s (+3.0v~3.3V)
Ground for I/O’s
Not connected
V
CC
NC
V
CCQ
NC
I/O
1
V
SSQ
NC
NC
V
CCQ
NC
I/O
2
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356404V-01
V
SS
NC
V
SSQ
NC
I/O
4
V
CCQ
NC
NC
V
SSQ
NC
I/O
3
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
I/O
1
–I/O
4
DQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3256(16/80/40)4VD Rev. 1.9 August 2008
5
单片机
