V58C2256(804/404/164)SA
HIGH PERFORMANCE 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
5B
DDR400
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
7.5 ns
5ns
5ns
200 MHz
5
DDR400
7.5 ns
6ns
5ns
200 MHz
6
DDR333
7.5 ns
6 ns
-
166 MHz
7
DDR266
7.5ns
7ns
-
143 MHz
Features
■
High speed data transfer rates with system frequency
up to 200 MHz
■
Data Mask for Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 2.5, 3
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 8192 cycles/64 ms
■
Available in 66-pin 400 mil TSOP or 60 Ball FBGA
■
SSTL-2 Compatible I/Os
■
Double Data Rate (DDR)
■
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
■
Power Supply 2.5V ± 0.2V
■
Power Supply 2.6V ± 0.1V for DDR400
■
tRAS lockout supported
■
Concurrent auto precharge option is supported
*Note: (-5B) Supports PC3200 module with 2.5-3-3 timing
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-7) Supports PC2100 module with 2-2-2 timing
Description
The V58C2256(804/404/164)SA is a four bank DDR
DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x
4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The
V58C2256(804/404/164)SA achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 FBGA
•
CK Cycle Time (ns)
-5B
•
Power
-7
•
-5
•
-6
•
Std.
•
L
•
Temperature
Mark
Blank
V58C2256(804/404/164)SA Rev.1.8 March 2007
1
ProMOS TECHNOLOGIES
Part Number Information
1
2
3
4
5
6
7
8
9 10
11
12
13
14
15
V58C2256(804/404/164)SA
16 17 18
19
V
ProMOS
5 8
C
2
2 5 6 8 0
ORGANIZATION
& REFRESH
32Mx4, 4K : 12840
16Mx8, 4K : 12880
64Mx4, 8K : 25640
32Mx8, 8K : 25680
16Mx16, 8K : 25616
8Mx32, 4K : 25632
32Mx16, 8K : 51216
8Mx16, 4K : 12816
4
S
A
T
5
TEMPERATURE
BLANK:
0 - 70C
-40 - 85C
-40 - 125C
5D : 200MHz @CL2-3-3
4 : 250MHz @CL4-4-4
37 : 266MHz @CL4-4-4
36 : 275MHz @CL4-4-4
33 : 300MHz @CL4-4-4
3 : 333MHz @CL5-5-5
28 : 350MHz @CL5-5-5
PACKAGE
LEAD
PLATING
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
T
S
B
D
Z
R
E
F
H
I
J
M
N
P
RoHS
GREEN PACKAGE
DESCRIPTION
TSOP
FBGA
BGA
Die-stacked TSOP
Die-stacked FBGA
TYPE
58 : DDR
56 : MOBILE DDR
128Mx4, 8K : 51240
64Mx8, 8K : 51280
256Mx4, 8K : G0140
128Mx8, 8K : G0180
I:
E:
SPEED
8 : 125MHz @CL3-3-3
75 : 133MHz @CL2.5-3-3
7 : 133MHz @CL2-2-2
6 : 166MHz @CL2.5-3-3
64Mx16, 8K : G0116
CMOS
VOLTAGE
2:
1:
2.5 V
1.8 V
BANKS
2 : 2 BANKS
4 : 4 BANKS
8 : 8 BANKS
I/O
S: SSTL_2
REV LEVEL
A: 1st
C: 3rd
B: 2nd D: 4th
5 : 200MHz @CL3-3-3
5B : 200MHz @CL2.5-3-3
*RoHS: Restriction of Hazardous Substances
*GREEN: RoHS-compliant and Halogen-Free
V58C2256(804/404/164)SA Rev. 1.8 March 2007
2
ProMOS TECHNOLOGIES
60-Ball FBGA PIN OUT
(x4)
1
VSSQ
NC
NC
NC
NC
VREF
2
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
3
VSS
DQ3
NC
DQ2
DQS
DM
CK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ0
NC
DQ1
NC
NC
WE
RAS
BA1
A0
A2
VDD
8
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
V58C2256(804/404/164)SA
(x8)
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
3
VSS
DQ6
DQ5
DQ4
DQS
DM
CK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ1
DQ2
DQ3
NC
NC
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
X4 Device Ball Pattern
X8 Device Ball Pattern
(x16)
1
2
DQ15
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
3
VSS
DQ13
DQ11
DQ9
UDQS
UDM
CK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ2
DQ4
DQ6
8
DQ0
VSSQ
VDDQ
VSSQ
9
PIN A1 INDEX
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
VSSQ
DQ14
DQ12
DQ10
DQ8
VREF
1
2
3
A
B
C
D
E
F
G
H
J
K
L
M
7
8
9
LDQS VDDQ
LDM
WE
RAS
BA1
A0
A2
VDD
VDD
CAS
CS
BA0
A10/AP
A1
A3
X16 Device Ball Pattern
TOP VIEW
(See the ball through the package)
V58C2256(804/404/164)SA Rev. 1.8 March 2007
3
ProMOS TECHNOLOGIES
66 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
16Mb x 16
32Mb x 8
64Mb x 4
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
66 PIN TSOP (II)
13
(400mil x 875 mil)
14
15
Bank Address
BA0-BA1
16
17
Row Address
18
A0-A12
19
20
Auto Precharge
A10
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V58C2256(804/404/164)SA
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Names
CK, CK
CKE
CS
RAS
CAS
WE
DQS (UDQS, LDQS)
A
0
–A
12
BA0, BA1
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
Bank Select
V
SS
V
DDQ
V
SSQ
NC
VREF
DQ’s
DM (UDM, LDM)
V
DD
Data Input/Output
Data Mask
Power
(+2.5V and +2.6V for DDR400)
Ground
Power for I/O’s
(+2.5V and +2.6V for DDR400)
Ground for I/O’s
Not connected
Reference Voltage for Inputs
V58C2256(804/404/164)SA Rev. 1.8 March 2007
4
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SA
Block Diagram
Column Addresses
64M x 4
Row Addresses
A0 - A12, BA0, BA1
A0 - A9, A11, AP, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
Bank 1
8192 x 1024
x8
8192 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
8192 x 1024
x8
Column decoder
Sense amplifier & I(O) bus
8192 x 1024
x8
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
3
CKE
RAS
CAS
WE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DM
CK
CK
CS
DQS
V58C2256(804/404/164)SA Rev. 1.8 March 2007
5
