MOSEL VITELIC
V58C365164SAT
HIGH PERFORMANCE
3.3 VOLT 4M X 16 DDR SDRAM
4 BANKS X 1Mbit X 16
PRELIMINARY
55
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK2
)
183 MHz
5.5 ns
6 ns
6.5 ns
6
166 MHz
6 ns
6.5 ns
7ns
7
143 MHz
7 ns
7.5 ns
8ns
8
125 MHz
8 ns
9 ns
10ns
I
4 banks x 1Mbit x 16 organization
I
High speed data transfer rates with system
frequency up to 183 MHz
I
Data Mask for Write Control (DM)
I
Four Banks controlled by BA0 & BA1
I
Programmable CAS Latency: 2, 2.5, 3
I
Programmable Wrap Sequence: Sequential
or Interleave
I
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
I
Automatic and Controlled Precharge Command
I
Suspend Mode and Power Down Mode
I
Auto Refresh and Self Refresh
I
Refresh Interval: 4096 cycles/64 ms
I
Available in 66-pin 400 mil TSOP-II
I
SSTL-2 Compatible I/Os
I
Double Data Rate (DDR)
I
Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
I
On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
I
Differential clock inputs CLK and CLK
I
Power supply 3.3V ± 0.3V
Features
Description
The V58C365164SAT is a four bank DDR DRAM
organized as 4 banks x 1Mbit x 16. The
V58C365164SAT achieves high speed data transfer
rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
•
CLK Cycle Time (ns)
-55
•
Power
-8
•
-6
•
-7
•
Std.
•
L
•
Temperature
Mark
Blank
V58C365164SAT Rev. 1.3 April 2001
1
MOSEL VITELIC
66 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V58C365164SAT
Pin Names
CLK, CLK
CKE
CS
RAS
CAS
WE
UDQS, LDQS
A
0
–A
11
BA0, BA1
DQ
0
–DQ
15
UDM, LDM
V
DD
V
SS
V
DDQ
V
SSQ
NC
V
REF
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+2.5V)
Ground for I/O’s
Not connected
Reference Voltage for Inputs
64M
DDR SDRAM
V58C365164SAT Rev. 1.3 April 2001
2
MOSEL VITELIC
Capacitance*
T
A
= 0 to 70
°
C, V
CC
= 3.3 V
±
0.3 V, f = 1 Mhz
Symbol Parameter
C
I1
C
I2
C
IO
C
CLK
Input Capacitance (A0 to A11)
Input Capacitance
RAS, CAS, WE, CS, CKE
Output Capacitance (DQ)
Input Capacitance (CCLK, CLK)
V58C365164SAT
Absolute Maximum Ratings*
Max. Unit
5
5
pF
pF
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (V
CC
+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ...........................................1.6 W
Data out current (short circuit).......................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
6.5
4
pF
pF
*
Note:
Capacitance is sampled and not 100% tested.
Block Diagram
Column Addresses
A0 - A7, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
Bank 1
4096 x 256
x 16 bit
4096 x 256
x 16 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 256
x 16 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 256
x 16 bit
Input buffer
Output buffer
Control logic & timing generator
I/Q
0
-IQ
15
CKE
RAS
CAS
WE
CS
CLK, CLK
DLL
Strobe
Gen.
Data Strobe
UDM
LDM
CLK
CLK
DQS
V58C365164SAT Rev. 1.3 April 2001
3
MOSEL VITELIC
Signal Pin Description
Pin
CLK
CLK
CKE
V58C365164SAT
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
Active High Active on both edges for data input and output.
Center aligned to input data
Edge aligned to output data
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will be precharged
simultaneously regardless of state of BA0 and BA1.
CS
Input
Pulse
RAS, CAS
WE
DQS
Input
Pulse
Input/
Output
Pulse
A0 - A11
Input
Level
BA0,
BA1
DQx
Input
Level
—
Selects which bank is to be active.
Input/
Output
Input
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DM
Pulse
Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input
data to be written if it is low but blocks the write operation if is high.
Power and ground for the input buffers and the core logic.
VDD, VSS Supply
VDDQ
VSSQ
VREF
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
SSTL Reference Voltage for Inputs
Input
Level
—
V58C365164SAT Rev. 1.3 April 2001
4
MOSEL VITELIC
Functional Description
V58C365164SAT
I
Power-Up Sequence
The following sequence is required for POWER UP.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.
4. Precharge all banks.
5. Issue EMRS to enable DLL.(To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0
and “Low” to all of the rest address pins, A1~A11 and BA1)
6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is
required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command to initialize device operation.
Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it,
the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Power up Sequence & Auto Refresh(CBR)
0
CK, CK
••
••
2 Clock min.
2 Clock min.
EMRS
MRS
DLL Reset
precharge
ALL Banks
1
2
3
4
5
6
7
8
9
10
••
11
12
13
14
••
15
16
17
18
19
t
RP
1st Auto
Refresh
t
RFC
••
••
2nd Auto
Refresh
t
RFC
••
••
2 Clock min.
Mode
Register Set
Any
Command
Command
200
µS
Power up
to 1st command
precharge
ALL Banks
min. 200 Cycle
4
5
6
7
8
8
Extended Mode Register Set (EMRS)
The extended mode register stores the data for enabling or disabling DLL. The default value of the extend-
ed mode register is not defined, therefore the extended mode register must be written after power up for en-
abling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and
high on BA
0
(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register). The state of address pins A
0
~ A
11
and BA
1
in the same cycle as CS, RAS,
CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the
write operation in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A
0
is used
for DLL enable or disable. “High” on BA
0
is used for EMRS. All the other address pins except A
0
and BA
0
must be set to low for proper EMRS operation. A
1
is used at EMRS to indicate I/O strength A
1
= 0 full strength,
A
1
= 1 half strength. Refer to the table for specific codes.
V58C365164SAT Rev. 1.3 April 2001
5
