V58C2512(804/404/164)SB
HIGH PERFORMANCE 512 Mbit DDR SDRAM
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 8Mbit X 16 (164)
5
DDR400
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
6ns
5ns
200 MHz
6
DDR333
6ns
-
166 MHz
75
DDR266
7.5ns
-
133 MHz
Features
■
High speed data transfer rates with system frequency
up to 200MHz
■
Data Mask for Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2.5, 3
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 8192 cycles/64 ms
■
Available in 60 Ball FBGA AND 66 Pin TSOP II
■
SSTL-2 Compatible I/Os
■
Double Data Rate (DDR)
■
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
■
Power Supply 2.5V ± 0.2V
■
Power Supply 2.6V ± 0.1V for DDR400
■
tRAS lockout supported
■
Concurrent auto precharge option is supported
*Note:
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-75) Supports PC2100 module with 2.5-3-3 timing
Description
The V58C2512(804/404/164)SB is a four bank DDR
DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x
32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The
V58C2512(804/404/164)SB achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
V58C2512(804/404/164)SB Rev.1.3 April 2006
Package Outline
JEDEC 66 TSOP II
60 FBGA
•
CK Cycle Time (ns)
-5
•
Power
Std.
•
-6
•
-75
•
L
•
Temperature
Mark
Blank
1
ProMOS TECHNOLOGIES
Part Number Information
1
2
3
4
5
6
7
8
9 10
11
12
13
14
V58C2512(804/404/164)SB
15
16 17 18
19
V
ProMOS
5 8
C
2
5 1 2 8 0
ORGANIZATION
& REFRESH
32Mx4, 4K : 12840
16Mx8, 4K : 12880
64Mx4, 8K : 25640
32Mx8, 8K : 25680
16Mx16, 8K : 25616
8Mx32, 4K : 25632
32Mx16, 8K : 51216
8Mx16, 4K : 12816
4
S
B
I
5
TEMPERATURE
BLANK:
0 - 70C
-40 - 85C
-40 - 125C
5D : 200MHz @CL2-3-3
4 : 250MHz @CL4-4-4
37 : 266MHz @CL4-4-4
36 : 275MHz @CL4-4-4
33 : 300MHz @CL4-4-4
3 : 333MHz @CL5-5-5
28 : 350MHz @CL5-5-5
PACKAGE
LEAD
PLATING
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
T
S
B
D
Z
R
E
F
H
I
J
M
N
P
RoHS
GREEN PACKAGE
DESCRIPTION
TSOP
FBGA
BGA
Die-stacked TSOP
Die-stacked FBGA
TYPE
58 : DDR
56 : MOBILE DDR
128Mx4, 8K : 51240
64Mx8, 8K : 51280
256Mx4, 8K : G0140
128Mx8, 8K : G0180
I:
E:
SPEED
8 : 125MHz @CL3-3-3
75 : 133MHz @CL2.5-3-3
7 : 133MHz @CL2-2-2
6 : 166MHz @CL2.5-3-3
64Mx16, 8K : G0116
CMOS
VOLTAGE
2:
1:
2.5 V
1.8 V
BANKS
2 : 2 BANKS
4 : 4 BANKS
8 : 8 BANKS
I/O
S: SSTL_2
REV LEVEL
A: 1st
B: 2nd
C: 3rd
D: 4th
5 : 200MHz @CL3-3-3
5B : 200MHz @CL2.5-3-3
*RoHS: Restriction of Hazardous Substances
*GREEN: RoHS-compliant and Halogen-Free
V58C2512(804/404/164)SB Rev. 1.3 April 2006
2
ProMOS TECHNOLOGIES
60-Ball FBGA PIN OUT
V58C2512(804/404/164)SB
(x4)
1
V
SSQ
NC
NC
NC
NC
V
REF
2
NC
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
CK
A
12
A
11
A
8
A
6
A
4
3
V
SS
DQ
3
NC
DQ
2
DQS
DM
CK
CKE
A
9
A
7
A
5
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
7
V
DD
DQ
0
NC
DQ
1
NC
NC
WE
RAS
BA
1
A
0
A
2
V
DD
8
NC
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
CAS
CS
BA
0
AP/A
10
A
1
A
3
9
V
DDQ
NC
NC
NC
NC
NC
(x8)
1
V
SSQ
NC
NC
NC
NC
V
REF
2
DQ
7
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
CK
A
12
A
11
A
8
A
6
A
4
3
V
SS
DQ
6
DQ
5
DQ
4
DQS
DM
CK
CKE
A
9
A
7
A
5
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
7
V
DD
DQ1
DQ2
DQ3
NC
NC
WE
RAS
BA
1
A
0
A
2
V
DD
8
DQ
0
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
CAS
CS
BA
0
AP/A
10
A
1
A
3
9
V
DDQ
NC
NC
NC
NC
NC
X4 Device Ball Pattern
X8 Device Ball Pattern
(x16)
1
V
SSQ
2
DQ
15
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
CK
A
12
A
11
A
8
A
6
A
4
3
V
SS
DQ
13
DQ
11
DQ
9
UDQS
UDM
CK
CKE
A
9
A
7
A
5
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
7
V
DD
DQ
2
DQ
4
DQ
6
LDQS
LDM
WE
RAS
BA
1
A
0
A
2
V
DD
8
DQ
0
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
CAS
CS
BA
0
AP/A
10
A
1
A
3
9
PIN A1 INDEX
1
2
3
A
B
C
D
E
F
G
H
J
K
L
M
TOP VIEW
(See the ball through the package)
7
8
9
V
DDQ
DQ
1
DQ
3
DQ
5
DQ
7
NC
DQ
14
DQ
12
DQ
10
DQ
8
V
REF
X16 Device Ball Pattern
V58C2512(804/404/164)SB Rev. 1.3 April 2006
3
ProMOS TECHNOLOGIES
66 Pin Plastic TSOP-II
PIN CONFIGURATION
32Mb x 16
64Mb x 8
128Mb x 4
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
A
0
A
1
A
2
A
3
V
DD
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
A
0
A
1
A
2
A
3
V
DD
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
66 PIN TSOP (II)
13
(400mil x 875 mil)
14
15
Bank Address
BA
0
-BA
1
16
17
Row Address
18
A
0
-A
12
19
20
Auto Precharge
A
10
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V58C2512(804/404/164)SB
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
AP/A
10
AP/A
10
Pin Names
CK, CK
CKE
CS
RAS
CAS
WE
DQS (UDQS, LDQS)
A
0
–A
12
BA
0
, BA
1
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
Bank Select
V
SS
V
DDQ
V
SSQ
NC
DQ’s
DM (UDM, LDM)
V
DD
Data Input/Output
Data Mask
Power
(+2.5V and +2.6V for DDR400)
Ground
Power for I/O’s
(+2.5V and +2.6V for DDR400)
Ground for I/O’s
Not connected
Reference Voltage for Inputs
V58C2512(804/404/164)SB Rev. 1.3 April 2006
4
V
REF
ProMOS TECHNOLOGIES
Block Diagram
Column Addresses
A
0
- A9, A
11
, AP, BA
0
, BA
1
V58C2512(804/404/164)SB
64M x 8
Row Addresses
A
0
- A
12
, BA
0
, BA
1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
8192 x 2048
8192 x 2048
Column decoder
Sense amplifier & I(O) bus
8192 x 2048
Column decoder
Sense amplifier & I(O) bus
8192 x 2048
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
7
CKE
RAS
CAS
WE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DM
CK
CK
CS
DQS
V58C2512(804/404/164)SB Rev. 1.3 April 2006
5
嵌入式系统
