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V59C1512804QAJ-3

64MX8 DDR DRAM, 0.45ns, PBGA60, GREEN, MO-207, FBGA-60

器件类别：存储    存储   

厂商名称：ProMOS Technologies Inc

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参数 预览 参数对比
器件参数
参数名称
属性值
厂商名称
ProMOS Technologies Inc
零件包装代码
DSBGA
包装说明
GREEN, MO-207, FBGA-60
针数
60
Reach Compliance Code
unknown
访问模式
FOUR BANK PAGE BURST
最长访问时间
0.45 ns
其他特性
AUTO/SELF REFRESH
JESD-30 代码
R-PBGA-B60
长度
12.5 mm
内存密度
536870912 bit
内存集成电路类型
DDR DRAM
内存宽度
8
功能数量
1
端口数量
1
端子数量
60
字数
67108864 words
字数代码
64000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
64MX8
封装主体材料
PLASTIC/EPOXY
封装代码
TFBGA
封装形状
RECTANGULAR
封装形式
GRID ARRAY, THIN PROFILE, FINE PITCH
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
1.9 V
最小供电电压 (Vsup)
1.7 V
标称供电电压 (Vsup)
1.8 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子形式
BALL
端子节距
0.8 mm
端子位置
BOTTOM
宽度
10 mm
文档预览
V59C1512(404/804/164)QA
HIGH PERFORMANCE 512 Mbit
DDR2 SDRAM
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 8Mbit X 16 (164)
5
DDR2-400
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK4
)
Clock Cycle Time (t
CK5
)
System Frequency (f
CK max
)
5ns
5ns
5ns
200 MHz
37
DDR2-533
5ns
3.75ns
3.75ns
266 MHz
PRELIMINARY
3
DDR2-667
5ns
3.75ns
3ns
333 MHz
Features
■
High speed data transfer rates with system frequency
up to 333 MHz
■
Posted CAS
■
Programmable CAS Latency: 3, 4 and 5
■
Programmable Additive Latency:0, 1, 2, 3 and 4
■
Write Latency=Read Latency-1
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 7.8 us (8192 cycles/64 ms)
■
OCD (Off-Chip Driver Impendance Adjustment)
■
ODT (On-Die Termination)
■
Weak Strength Data-Output Driver Option
■
Bidirectional differential Data Strobe (Single-ended
data-strobe is an optional feature)
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
■
JEDEC Power Supply 1.8V ± 0.1V
■
VDDQ=1.8V ± 0.1V
■
Available in 60-ball FBGA for x4 and x8 component or
84 ball FBGA for x16 component
■
PASR Partial Array Self Refresh
Available Speed Grade
-5 (DDR2-400) @CL3-3-3
-37 (DDR2-533) @CL4-4-4
-3 (DDR2-667) @CL5-5-5
Description
The V59C1512(404/804/164)QA is a four bank DDR
DRAM organized as 4 banks x 32Mbit x 4 (404), 4 banks x
16Mbit x 8 (804), or 4 banks x 8Mbit x 16 (164). The
V59C1512(404/804/164)QA achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
The chip is designed to comply with the following key
DDR2 SDRAM features:(1) posted CAS with additive la-
tency, (2)write latency=read latency-1, (3)Off-chip Driv-
er(OCD) impedance adjustment, (4) On Die Termination.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
s are synchronized with a pair of bidirectional strobes
(DQS, DQS) in a source synchronous fashion.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
60 ball FBGA
84 ball FBGA
•
CK Cycle Time (ns)
-5
•
Power
Std.
•
-37
•
-3
•
L
•
Temperature
Mark
Blank
V59C1512(404/804/164)QA Rev.1.0 September 2005
1
ProMOS TECHNOLOGIES
DDR Part Number
V59C1512(404/804/164)QA
V
ProMOS
5 9
C
1
5 1 2 8 0
ORGANIZATION
& REFRESH
64Mx4, 8K : 25640
32Mx8, 8K : 25680
128Mx4, 8K : 51240
32Mx16, 8K : 51216
16Mx32, 8K : 51232
64Mx16, 8K : G0116
16Mx16, 8K : 25616
4
Q
A
F
5
TEMPERATURE
BLANK:
0 - 70C
-40 - 85C
-40 - 125C
TYPE
59 : DDR2
CMOS
64Mx8, 8K : 51280
256Mx4, 8K : G0140
128Mx8, 8K : G0180
I:
E:
SPEED
5 : 200MHz @CL3-3-3
37 : 266MHz @CL4-4-4
3 : 333MHz @CL5-5-5
25 : 400MHz @CL6-6-6
VOLTAGE
1:
1.8 V
BANKS
4 : 4 BANKS
8 : 8 BANKS
I/O
Q: SSTL_18
REV LEVEL
A: 1st
C: 3rd
F
B: 2nd D: 4th
PACKAGE
RoHS
GREEN PACKAGE
DESCRIPTION
J
FBGA
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
* RoHS: Restriction of Hazardous Substances
* Green: RoHS-compliant and Halogen-free
512Mb Addressing
Confi gura tion
# of Bank
Bank Address
Auto precharge
Row Address
Column Address
128Mb x 4
4
BA0,BA1
A
10
/AP
A
0
~ A
13
A
0
~ A
9,
A
11
64Mb x 8
4
BA0,BA1
A
10
/AP
A
0
~ A
13
A
0
~ A
9
32Mb x1 6
4
BA0,BA1
A
10
/AP
A
0
~ A
12
A
0
~ A
9
V59C1512(404/804/164)QA Rev. 1.0 September 2005
2
ProMOS TECHNOLOGIES
V59C1512(404/804/164)QA
x4 pack age pinout (Top View) : 60ball FBGA Package
1
VDD
NC
2
NC
VSSQ
3
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
DQS
VSSQ
DQ0
VSSQ
8
9
VDDQ
NC
VDDQ
NC
VDD
ODT
VDDQ DQ1
NC
VSSQ
VDDL VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
VSSDL CK
RAS
CAS
A2
A6
A11
NC
CK
CS
A0
A4
A8
A13
VDD
VSS
Notes:
B1, B9, D1, D9 = NC for x4 organization.
Pins B3 has identical capacitance as pins B7.
VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device from
VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x4)
: Populated Ball
+
: Depopulated Ball
Top View (See the balls through the Package)
1
A
B
C
D
E
F
G
H
J
K
L
2
3
4
5
6
7
8
9
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V59C1512(404/804/164)QA Rev. 1.0 September 2005
3
ProMOS TECHNOLOGIES
V59C1512(404/804/164)QA
x8 package pinout (Top View) : 60ball FBGA Package
1
VDD
DQ6
VDDQ
DQ4
VDDL
2
NU/
RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
3
VSS
DM/
RDQS
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VSS
VDD
9
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7 and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS
& DQS and input masking function is disabled.
3. The function of DM or RDQS/RDQS are enabled by EMRS command.
4. VDDL and VSSDL are power and ground for the DLL. It is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x8)
: Populated Ball
+
: Depopulated Ball
Top View (See the balls through the Package)
1
A
B
C
D
E
F
G
H
J
K
L
2
3
4
5
6
7
8
9
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V59C1512(404/804/164)QA Rev. 1.0 September 2005
4
ProMOS TECHNOLOGIES
V59C1512(404/804/164)QA
x16 package pinou t (Top View) : 84 ball FBGA Packa ge
1
VDD
UDQ6
VDDQ
UDQ4
VDD
LDQ6
VDDQ
LDQ4
VDDL
2
NC
VSSQ
UDQ1
VSSQ
NC
VSSQ
LDQ1
VSSQ
VREF
CKE
3
VSS
UDM
VDDQ
UDQ3
VSS
LDM
VDDQ
LDQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7
VSSQ
UDQS
VDDQ
UDQ2
VSSQ
8
UDQS
VSSQ
UDQ0
VSSQ
LDQS
VSSQ
LDQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
9
VDDQ
UDQ7
VDDQ
UDQ5
VDDQ
LDQ7
VDDQ
LDQ5
VDD
ODT
LDQS
VDDQ
LDQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
NC
BA0
A10
VDD
VSS
A3
A7
VSS
VDD
A12
Notes:
VDDL and VSSDL are power and ground for the DLL. lt is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
1
2
3
4
5
6
7
8
9
Ball Locations (x16)
: Populated Ball
+
: Depo pul ated Ball
A
B
C
D
E
F
Top View
(See the balls through the Package)
G
H
J
K
L
M
N
P
R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V59C1512(404/804/164)QA Rev. 1.0 September 2005
5
查看更多>
参数对比
与V59C1512804QAJ-3相近的元器件有：V59C1512164QAJ-3、V59C1512164QAJ-37、V59C1512404QAJ-5、V59C1512804QAJ-5、V59C1512164QAJ-5、V59C1512804QAJ-37、V59C1512404QAJ-37、V59C1512404QAJ-3。描述及对比如下：
型号 V59C1512804QAJ-3 V59C1512164QAJ-3 V59C1512164QAJ-37 V59C1512404QAJ-5 V59C1512804QAJ-5 V59C1512164QAJ-5 V59C1512804QAJ-37 V59C1512404QAJ-37 V59C1512404QAJ-3
描述 64MX8 DDR DRAM, 0.45ns, PBGA60, GREEN, MO-207, FBGA-60 32MX16 DDR DRAM, 0.45ns, PBGA84, GREEN, MO-207, FBGA-84 32MX16 DDR DRAM, 0.5ns, PBGA84, GREEN, MO-207, FBGA-84 128MX4 DDR DRAM, 0.6ns, PBGA60, GREEN, MO-207, FBGA-60 64MX8 DDR DRAM, 0.6ns, PBGA60, GREEN, MO-207, FBGA-60 32MX16 DDR DRAM, 0.6ns, PBGA84, GREEN, MO-207, FBGA-84 64MX8 DDR DRAM, 0.5ns, PBGA60, GREEN, MO-207, FBGA-60 128MX4 DDR DRAM, 0.5ns, PBGA60, GREEN, MO-207, FBGA-60 128MX4 DDR DRAM, 0.45ns, PBGA60, GREEN, MO-207, FBGA-60
厂商名称 ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc ProMOS Technologies Inc
零件包装代码 DSBGA DSBGA DSBGA DSBGA DSBGA DSBGA DSBGA DSBGA DSBGA
包装说明 GREEN, MO-207, FBGA-60 TFBGA, GREEN, MO-207, FBGA-84 TFBGA, GREEN, MO-207, FBGA-60 TFBGA, GREEN, MO-207, FBGA-60 TFBGA, GREEN, MO-207, FBGA-60
针数 60 84 84 60 60 84 60 60 60
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown unknow
访问模式 FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 0.45 ns 0.45 ns 0.5 ns 0.6 ns 0.6 ns 0.6 ns 0.5 ns 0.5 ns 0.45 ns
其他特性 AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 代码 R-PBGA-B60 R-PBGA-B84 R-PBGA-B84 R-PBGA-B60 R-PBGA-B60 R-PBGA-B84 R-PBGA-B60 R-PBGA-B60 R-PBGA-B60
长度 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm 12.5 mm
内存密度 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bi
内存集成电路类型 DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM
内存宽度 8 16 16 4 8 16 8 4 4
功能数量 1 1 1 1 1 1 1 1 1
端口数量 1 1 1 1 1 1 1 1 1
端子数量 60 84 84 60 60 84 60 60 60
字数 67108864 words 33554432 words 33554432 words 134217728 words 67108864 words 33554432 words 67108864 words 134217728 words 134217728 words
字数代码 64000000 32000000 32000000 128000000 64000000 32000000 64000000 128000000 128000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
组织 64MX8 32MX16 32MX16 128MX4 64MX8 32MX16 64MX8 128MX4 128MX4
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
最大供电电压 (Vsup) 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V
最小供电电压 (Vsup) 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V 1.7 V
标称供电电压 (Vsup) 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
表面贴装 YES YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子形式 BALL BALL BALL BALL BALL BALL BALL BALL BALL
端子节距 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
端子位置 BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
宽度 10 mm 10 mm 10 mm 10 mm 10 mm 10 mm 10 mm 10 mm 10 mm
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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