V62C1802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 25mA at 70ns
- Stand-by: 10
µ
A
(CMOS input/output)
2
µ
A
CMOS input/output, L version
• Single + 1.8 to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
Functional Description
The V62C1802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1 , an active HIGH CE2, an act-
ive LOW OE , and Tri-state I/O’s. This device has an auto-
matic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1 ) with Write Enable (WE ) LOW, and Chip En-
able 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1 ) with Output Enable
(OE ) LOW while Write Enable (WE ) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-imped-
ance state when the device is deselected: the outputs are
disabled during a write cycle.
The V62C1802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1802048L is available in
a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP
A
11
A
9
A
8
A
13
WE
CE
2
A
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
INPUT BUFFER
A
0
ROW DECODER
SENSE AMP
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A9
I/O8
Vcc
A17
A
16
A
14
A
12
A
7
A
6
Cell Array
I/O1
A
5
A
4
COLUMN DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
CONTROL
CIRCUIT
OE
WE
CE1
CE2
1
REV. 1.2
May
2001 V62C1802048L(L)
V62C1802048L(L)
Absolute Maximum Ratings *
Parameter
Voltage on Any Pin Relative to Gnd
Power Dissipation
Storage Temperature (Plastic)
Temperature Under Bias
Symbol
Vt
P
T
Tstg
Tbias
Minimum
-0.5
−
-55
-40
Maximum
4.6
1.0
+150
+85
Unit
V
W
0
C
0
C
* Note:
Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
X
L
H
X
Data
High-Z
High-Z
Data Out
High-Z
Data In
Standby
Standby
Active, Read
Mode
Active, Output Disable
Active, Write
* Key:
X = Don’t Care, L = Low, H = High
Recommended Operating Conditions
(T
A
= 0
0
C to +70
0
C / -40
0
C to 85
0
C
**
)
Parameter
Supply Voltage
Symbol
V
CC
Gnd
V
IH
V
IL
Min
1.8
0.0
1.6
-0.5*
Typ
2.0
0.0
-
-
Max
2.2
0.0
V
CC
+ 0.2
0.4
Unit
V
V
V
V
Input Voltage
*
V
IL
min = -1.0V for pulse width less than t
RC
/2.
**
For Industrial Temperature.
2
REV. 1.2
May
2001 V62C1802048L(L)
V62C1802048L(L)
DC Operating Characteristics
(V
cc
= 1.8 to 2.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to 85
0
C)
Parameter
Input Leakage Current
Output Leakage
Current
Operating Power
Supply Current
Average Operating
Current
Sym
Test Conditions
V
cc
= Max,
V
in
= Gnd to V
cc
CE1 = V
IH
or CE2 = V
IL
V
cc
= Max, V
OUT
= Gnd to V
cc
CE1 = V
IL
, CE2 = V
IH
V
IN
= V
IH
or V
IL
, I
OUT
= 0 mA
CE1 = V
IL
, CE2 = V
IH
I
OUT
= 0mA,
Min Cycle, 100% Duty
CE1 = 0.2V ,
CE2 =V
cc
- 0.2V
I
OUT
= 0mA,
Cycle Time=1µs, 100% Duty
-70
-
-
-
-
1
1
3
20
-
-
-
-
-85
1
1
3
20
-
-
-
-
-100
1
1
3
15
-
-
-
-
-150
1
1
3
15
Min Max Min Max Min Max Min Max
Unit
µA
µA
mA
I
I
LI
I
I
I
LO
I
I
CC
I
CC1
mA
I
CC2
-
3
-
3
-
3
-
3
mA
Standby Power Supply
Current (TTL Level)
Standby Power Supply
Current (CMOS Level)
I
SB
I
SB1
CE1 = V
IH
or CE2 = V
IL
CE1 > V
cc
- 0.2V or
CE2 < 0.2V, f = 0
V
IN
< 0.2V or
V
IN
> V
cc
- 0.2V
I
OL
= 2 mA
I
OH
= -1 mA
-
-
0.3
10
2
0.4
-
-
-
-
-
1.6
0.3
10
2
0.4
-
-
-
-
-
1.6
0.3
10
2
0.4
-
-
-
-
-
1.6
0.3
10
2
0.4
-
mA
µA
µA
V
V
L
-
-
1.6
Output Low Voltage
Output High Voltage
V
OL
V
OH
Capacitance
(f = 1MHz, T
A
= 25
0
C)
Parameter*
Symbol
Input Capacitance
I/O Capacitance
Test Condition
V
in
= 0V
V
in
= V
out
= 0V
Max
7
8
Unit
pF
pF
C
in
C
I/O
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.4V to 1.6V
5ns
50% of input level
(VIL+VIH)/2
TTL
C
L
*
Output Load Condition
70ns/85 ns
C
L
= 30pf + 1TTL Load
Load 100ns/150 ns
C
L
= 100pf + 1TTL Load
Figure A.
* Including Scope and Jig Capacitance
3
REV. 1.2
May
2001 V62C1802048L(L)
V62C1802048L(L)
Read Cycle
(3,9)
(V
cc
= 1.8 to2.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Power-Up Time
Power-Down Time
Symbol
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CLZ
t
CHZ
t
OLZ
t
OHZ
t
PU
t
PD
70
-
-
-
10
10
-
5
-
0
-
-70
-
70
70
40
-
-
30
-
25
-
70
85
-
-
-
10
10
-
5
-
0
-
-85
-
85
85
40
-
-
35
-
30
-
85
-100
100
-
-
-
10
10
-
5
-
0
-
-
100
100
50
-
-
40
-
35
-
100
-150
150
-
-
-
10
10
-
5
-
0
-
-
150
150
70
-
-
50
-
40
-
150
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Min Max Min Max Min Max Min Max
4,5
4,5
4,5
4,5
5
5
Write Cycle
(3,11)
(V
cc
= 1.8 to 2.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovering Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
WZ
t
OW
70
60
60
0
50
0
30
0
-
5
-70
-85
-100
-150
Unit
-
-
-
-
-
-
-
-
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Min Max Min Max Min Max Min Max
-
-
-
-
-
-
-
-
30
-
85
70
70
0
60
0
35
0
-
5
-
-
-
-
-
-
-
-
35
-
100
80
80
0
70
0
40
0
-
5
-
-
-
-
-
-
-
-
40
-
150
120
120
0
100
0
60
0
-
5
4,5
4,5
4
REV. 1.2
May
2001 V62C1802048L(L)
V62C1802048L(L)
Timing Waveform of Read Cycle 1
(3,6,7,9)
(Address Controlled)
t
RC
Address
t
AA
D
OUT
t
OH
Data Valid
Timing Waveform of Read Cycle 2
(5,6,8,9)
(CE1 Controlled)
t
RC
CE1
OE
t
OLZ
D
OUT
t
ACE
t
OE
t
OHZ
t
CHZ
Data Valid
t
CLZ
Supply Current
t
PD
I
CC
50%
50%
t
PU
I
SB
Timing Waveform of Read Cycle 3
(3,6,8,9)
(CE2 Controlled)
t
RC
CE2
OE
t
OLZ
D
OUT
t
OE
t
OHZ
t
CHZ
Data Valid
t
ACE
t
CLZ
Supply Current
t
PD
I
CC
50%
50%
t
PU
I
SB
5
REV. 1.2
May
2001 V62C1802048L(L)
