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V63C31321024-7Q

Standard SRAM, 32KX32, 7ns, CMOS, PQFP100

器件类别：存储    存储   

厂商名称：Mosel Vitelic Corporation ( MVC )

厂商官网：http://www.moselvitelic.com

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参数 预览 参数对比
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Mosel Vitelic Corporation ( MVC )
包装说明
QFP, QFP100,.7X.9
Reach Compliance Code
unknown
最长访问时间
7 ns
I/O 类型
COMMON
JESD-30 代码
R-PQFP-G100
JESD-609代码
e0
内存密度
1048576 bit
内存集成电路类型
STANDARD SRAM
内存宽度
32
端子数量
100
字数
32768 words
字数代码
32000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
32KX32
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
QFP
封装等效代码
QFP100,.7X.9
封装形状
RECTANGULAR
封装形式
FLATPACK
并行/串行
PARALLEL
电源
3.3 V
认证状态
Not Qualified
最大待机电流
0.005 A
最小待机电流
3.14 V
最大压摆率
0.25 mA
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.635 mm
端子位置
QUAD
Base Number Matches
1
文档预览
MOSEL VITELIC
V63C31321024
32K X 32 CMOS
SYNCHRONOUS BURST
PIPELINED SRAM
PRELIMINARY
Features
s
s
s
s
s
s
s
s
s
High-speed clock access time: 5/6/7/8ns
Single 3.3V power supply
Synchronous operation
Individual byte write control and global write
Internal registers for address, data, and controls
Output data registers
Asynchronous Output Enable
Supports snooze mode (low-power state)
Internal burst counter supports interleaved or lin-
ear burst mode
s
Available in 100-pin PQFP/TQFP
Functional Description
The V63C31321024 is a high-speed synchro-
nous burst pipelined CMOS SRAM organized as
32,768 words by 32 bits that supports both i486/
Pentium™ Interleaved mode and 680X0/Power
PC™ linear mode address pipelining. Control is
achieved through the use of the LBO pin.
Burst operations can be initiated with either the
address status processor (ADSP) or address status
cache controller (ADSC) inputs. Subsequently burst
addresses can be internally generated as controlled
by the burst advance (ADV) input.
The V63C31321024 operates on a single 3.3V
power supply and is ideally suited for applica-
tions that require high-speed, low-power and
wide-bit configuration in secondary cache designs.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
Package Outline
Q
•
U
•
5
•
Access Time (ns)
6
•
7
•
8
•
Power
Std.
•
Temperature
Mark
Blank
V63C31321024 Rev. 0.3 October 1997
1
MOSEL VITELIC
Block Diagram
LBO
ADV
CLK
A0 to A14
ADSC
V63C31321024
A0'
15
Address
Registers
CLR
Binary
Counter
A0
A1'
A1
13
15
15
GW
BWE
BW0
Byte 0
Write
Register
Byte 0
Write
Driver
8
BW1
Byte 1
Write
Register
Byte 1
Write
Driver
8
32Kx8x4
Memory
Array
8
BW2
Byte 2
Write
Register
Byte 2
Write
Driver
BW3
CE3
CE2
CE1
Byte 3
Write
Register
4
Enable
Register
32
4
Byte 3
Write
Driver
8
32
ADSP
OE
Enable
Delay
Register
Address
Registers
Input
Registers
ZZ
Sleep
Control
32
I/O0 to I/O31
V63C31321024 Rev. 0.3 October 1997
2
MOSEL VITELIC
Ordering Information
V
6
3
C
–
V63C31321024
FAMILY
DEVICE
BLANK (STANDARD)
PWR.
SPEED
TEMP.
BLANK (0°C to 70°C)
PKG
5
6
7
8
(5 ns)
(6 ns)
(7 ns)
(8 ns)
Q (PQFP)
U (TQFP)
31321024-08
100-Pin QFP/TQFP
PIN CONFIGURATION
NC
I/O16
I/O17
V
CCQ
GNDQ
I/O18
I/O19
I/O20
I/O21
GNDQ
V
CCQ
I/O22
I/O23
NC
V
CC
NC
GND
I/O24
I/O25
V
CCQ
GNDQ
I/O26
I/O27
I/O28
I/O29
GNDQ
V
CCQ
I/O30
I/O31
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE1
CE2
BW3
BW2
BW1
BW0
CE3
V
CC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O15
I/O14
V
CCQ
GNDQ
I/O13
I/O12
I/O11
I/O10
GNDQ
V
CCQ
I/O9
I/O8
GND
NC
V
CC
ZZ
I/O7
I/O6
V
CCQ
GNDQ
I/O5
I/O4
I/O3
I/O2
GNDQ
V
CCQ
I/O1
I/O0
NC
V63C31321024 Rev. 0.3 October 1997
LBO
A5
A4
A3
A2
A1
A0
NC
NC
GND
V
CC
NC
NC
A10
A11
A12
A13
A14
NC
NC
3
MOSEL VITELIC
Pin Names
Symbol
A0—A14
I/O
0
-I/O
31
CLK
CE1, CE2, CE3
GW
BWE
BW
0
-BW
3
OE
ADV
ADSC
ADSP
ZZ
LBO
V
CCQ
GNDQ
V
CC
GND
V63C31321024
Type
Input, Synchronous
I/O, Synchronous
Input, Clock
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Static
Hot Address
Data Inputs/Outputs
Processor Host Bus Clock
Chip Enables
Global Write
Description
Byte Write Enable from Cache Controller
Host BusByte Enables Used with BWE
Output Enable Input
Internal Burst Address Counter Advance
Address Status from CPU
Address Status from Chip Set
Snooze Pin for Low-Power State
This Mode Selects Burst Sequence
LOW for Linear or HIGH for interleaved
I/O Power Supply
I/O Ground
Power Supply
Ground
Absolute Maximum Ratings*
Core Supply Voltage to GND............. –0.5 to +4.6V
I/O Supply Voltage to GND................ –0.5 to +4.6V
Input/Output to
GND Potential ......... GNDQ–0.5 to V
CCQ
+0.5V
Allowable Power Dissipation .......................... 1.0W
Storage Temperature ...................... –65 to +150
°
C
Operating Temperature ......................... 0 to +70
°
C
Note:
Exposure to conditions beyond those listed under
Absolute Maximum Ratings
may adversely affect the life
and reliability of the device.
Capacitance
Symbol
C
IN
C
I/O
V
CC
= 3.3 V, T
A
= 25
°
C, f = 1 MHz
Parameter*
Input Capacitance
Input/Output
Capacitance
Conditions Max.
V
IN
= 0V
V
OUT
= 0V
6
8
Unit
pF
pF
* Note: These parameters are guaranteed by device
characterization and are not production tested.
V63C31321024 Rev. 0.3 October 1997
4
MOSEL VITELIC
Truth Table
Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
V63C31321024
Address
Used
No
No
No
No
No
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
CE1
1
0
0
0
0
0
0
X
X
1
1
X
X
1
1
X
1
0
X
1
X
1
CE2
X
X
0
X
0
1
1
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
CE3
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
ADSP
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
X
1
1
X
1
X
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
ADV
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
X
0
0
1
1
OE
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
Data
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D-OUT
Hi-Z
D-OUT
Hi-Z
D-Out
Hi-Z
D-OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Write
(1)
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
Notes:
1. For a detailed definition of read/write, see the Write Table (next page).
2. A “X” means “don’t care,” “1” means logic HIGH, and “0” means logic LOW.
3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled
synchronous to the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data
to setup the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM
data hold timing are met.
V63C31321024 Rev. 0.3 October 1997
5
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参数对比
与V63C31321024-7Q相近的元器件有：V63C31321024-6U、V63C31321024-7U、V63C31321024-8U、V63C31321024-5U、V63C31321024-8Q、V63C31321024-5Q、V63C31321024-6Q。描述及对比如下：
型号 V63C31321024-7Q V63C31321024-6U V63C31321024-7U V63C31321024-8U V63C31321024-5U V63C31321024-8Q V63C31321024-5Q V63C31321024-6Q
描述 Standard SRAM, 32KX32, 7ns, CMOS, PQFP100 Standard SRAM, 32KX32, 6ns, CMOS, PQFP100 Standard SRAM, 32KX32, 7ns, CMOS, PQFP100 Standard SRAM, 32KX32, 8ns, CMOS, PQFP100 Standard SRAM, 32KX32, 5ns, CMOS, PQFP100 Standard SRAM, 32KX32, 8ns, CMOS, PQFP100 Standard SRAM, 32KX32, 5ns, CMOS, PQFP100 Standard SRAM, 32KX32, 6ns, CMOS, PQFP100
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合
厂商名称 Mosel Vitelic Corporation ( MVC ) Mosel Vitelic Corporation ( MVC ) Mosel Vitelic Corporation ( MVC ) Mosel Vitelic Corporation ( MVC ) Mosel Vitelic Corporation ( MVC ) Mosel Vitelic Corporation ( MVC ) Mosel Vitelic Corporation ( MVC ) Mosel Vitelic Corporation ( MVC )
包装说明 QFP, QFP100,.7X.9 QFP, QFP100,.63X.87 QFP, QFP100,.63X.87 QFP, QFP100,.63X.87 QFP, QFP100,.63X.87 QFP, QFP100,.7X.9 QFP, QFP100,.7X.9 QFP, QFP100,.7X.9
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown
最长访问时间 7 ns 6 ns 7 ns 8 ns 5 ns 8 ns 5 ns 6 ns
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 代码 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100
JESD-609代码 e0 e0 e0 e0 e0 e0 e0 e0
内存密度 1048576 bit 1048576 bit 1048576 bit 1048576 bit 1048576 bit 1048576 bit 1048576 bit 1048576 bit
内存集成电路类型 STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM
内存宽度 32 32 32 32 32 32 32 32
端子数量 100 100 100 100 100 100 100 100
字数 32768 words 32768 words 32768 words 32768 words 32768 words 32768 words 32768 words 32768 words
字数代码 32000 32000 32000 32000 32000 32000 32000 32000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
组织 32KX32 32KX32 32KX32 32KX32 32KX32 32KX32 32KX32 32KX32
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 QFP QFP QFP QFP QFP QFP QFP QFP
封装等效代码 QFP100,.7X.9 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 QFP100,.7X.9 QFP100,.7X.9 QFP100,.7X.9
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 FLATPACK FLATPACK FLATPACK FLATPACK FLATPACK FLATPACK FLATPACK FLATPACK
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
电源 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
最大待机电流 0.005 A 0.005 A 0.005 A 0.005 A 0.005 A 0.005 A 0.005 A 0.005 A
最小待机电流 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V
最大压摆率 0.25 mA 0.25 mA 0.25 mA 0.25 mA 0.25 mA 0.25 mA 0.25 mA 0.25 mA
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.635 mm 0.635 mm 0.635 mm 0.635 mm 0.635 mm 0.635 mm 0.635 mm 0.635 mm
端子位置 QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD
Base Number Matches 1 1 1 1 1 1 1 1
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器件捷径:
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY
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