V826616B24SC
128 MB 200-PIN DDR UNBUFFERED
SODIMM 16M x 64
Features
■
JEDEC 200 Pin DDR Unbuffered Small-Outline,
Dual In-Line memory module (SODIMM);
16,777,216 x 64 bit organization.
■
Utilizes High Performance 16M x 16 DDR
SDRAM in TSOPII-66 Packages
■
Single +2.5V (± 0.2V) Power Supply
■
Single +2.6V (± 0.1V) Power Supply for DDR400
■
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■
Auto Refresh (CBR) and Self Refresh
■
All Inputs, Outputs are SSTL-2 Compatible
■
8192 Refresh Cycles every 64 ms
■
Serial Presence Detect (SPD)
■
DDR SDRAM Performance
Component Used -6
-7
Module Speed
-75
-8
D0
Description
The V826616B24SC memory module is
organized 16,777,216 x 64 bits in a 200 pin memory
module. The 16M x 64 memory module uses 4
ProMOS 16M x 16 DDR SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
t
CK
t
AC
Clock Frequency
166
143
133
125
(PC333) (PC266A) (PC266B) (PC200)
200
(max.)Clock Frequency (max.)
(PC400A)
D3
200
(PC400B)
C0
166
(PC333)
Units
MHz
ns
ns
ns
CLK
CLK
Clock Access Time
6
7
7.5
Clock Cycle
CAS Latency = 2.5Time CAS Latency = 2
Clock Cycle Time CAS Latency = 2.5
Clock Cycle Time CAS Latency = 3
8
7.5
5
5
3
3
7.5
6
5
3
3
7.5
6
-
3
3
t
CK
t
RCD
t
RP
tRCD parameter
tRP parameter
V826616B24SC Rev. 1.2 April 2006
1
ProMOS TECHNOLOGIES
Part Number Information
V826616B24SC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
V
ProMOS
TYPE
8 : DDR
8
2
6 6
1 6
DATA
DEPTH
16 : 16Mb
32 : 32 Mb
64 : 64 Mb
65 : 128 Mb
66 : 256 Mb
B
2
REFRESH
RATE
0: 4K
2: 8K
4
S
C
COMPONENT
REV LEVEL
I
W
PCB TYPE
-
D
3
G : GOLD_LEAD PLATING
W : GOLD_RoHS
L : LOW PROFILE_LEAD PLATING
X : LOW PROFILE_RoHS
VOLTAGE
2 : 2.5V
DATA WIDTH
& COMP DENSITY
65
66
67
68
69
73
74
75
76
77
X64 using 128M
X64 using 256M
X64 using 512M
X64 using 1G
X64 using 2G
X72 using 128M
X72 using 256M
X72 using 512M
X72 using 1G
X72 using 2G
MODULE TYPE
& COMP WIDTH
BANKS
4 : 4 Banks
COMPONENT PKG
LEAD
PLATING
T
S
D
Z
I
J
N
P
GREEN
PACKAGE
DESCRIPTION
TSOP
FBGA
Die-stacked TSOP
Die-stacked FBGA
BASED ON
184PIN DIMM
UNBUFFERED
184PIN DIMM
REGISTERED
200PIN
SO-DIMM
172PIN
Micro-DIMM
X4 X16 X8
I
N
V
J
O
B
K
U
G
M
I/O INTERFACE
S: SSTL_2
SPEED
B0 : PC2100B (133MHz @CL2.5-3-3)
B1 : PC2100A (133MHz @CL2-2-2)
C0 : PC2700 (166MHz @CL2.5-3-3)
D0 : PC3200 (200MHz @CL2.5-3-3)
D3 : PC3200 (200MHz @CL3-3-3)
*RoHS: Restriction of Hazardous Substances
*GREEN: RoHS-compliant and Halogen-Free
V826616B24SC Rev. 1.2 April 2006
2
ProMOS TECHNOLOGIES
Block Diagram
V826616B24SC
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
D0
D2
DQS1
DM1
DQS5
DM5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
D1
D3
DQS3
DM3
DQS7
DM7
*Clock Net Wiring
Dram1
BA0 - BA1
A0 - A12
RAS
CAS
CKE0
WE
BA0-BA1: DDR SDRAMs D0 - D3
A0-A13: DDR SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
CAS: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
Clock
Input
CK0/CK0
CK1/CK1
CK2/CK2
Clock Wiring
SDRAMs
2 SDRAMs
2 SDRAMs
NC
CK
CK
Card
Edge
R=120
Ω
±
5%
Cap
Dram3
Cap
V
DDSPD
V
DD
/V
DDQ
SPD
D0 - D3
D0 - D3
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
VREF
V
SS
V
DDID
D0 - D3
D0 - D3
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
SDA
be maintained as shown.
V826616B24SC Rev. 1.2 April 2006
3
ProMOS TECHNOLOGIES
Pin Configurations (Front Side/Back Side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
Front
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0
VSS
Key
V826616B24SC
Pin
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
Front
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2
VDD
CKE1
DU(A13)
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE
S0
DU
VSS
DQ32
DQ33
VDD
DQS4
Pin
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Front
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
DQ58
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
Back
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
Key
Pin
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
Back
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS
CAS
S1
DU
VSS
DQ36
DQ37
VDD
DM4
Pin
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
Notes:
*
These pins are not used in this module.
Pin Names
Pin
A0~A12
BA0~BA1
DQ0~DQ63
DQS0~DQS7
CK0~CK2, CK0~CK2,
CKE0
S0 , S1
RAS
CAS
WE
DM0~DM7
V826616B24SC Rev. 1.2 April 2006
Pin Description
Address Input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data - In Mask
Pin
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0~2
VDDID
NC
Pin Description
Power Supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power Supply for Reference
Serial EEPOM Power Supply (2.3V
to 3.6V)
Serial Data I/O
Serial Clock
Address in EEPROM
VDD Identification Flag
No Connection
4
ProMOS TECHNOLOGIES
Serial Presence Detect Information
Bin Sort:
D0 (PC3200 @ CL 2.5-3-3)
D3 (PC3200 @ CL 3-3-3 )
C0 (PC2700 @ CL 2.5-3-3)
V826616B24SC
Function Supported
Byte #
0
Hex value
D0
D3
80h
Function described
Defines # of Bytes written into serial memory at module manu-
facturer
Total # of Bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module Rows on this assembly
Data width of this assembly
.........Data width of this assembly
VDDQ and interface standard of this assembly
DDR SDRAM cycle time at highest CAS Latency
DDR SDRAM Access time from clock at highest CL
DIMM configuration type(Non-parity, Parity, ECC)
Refresh rate & type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column address
DDR SDRAM device attributes : Burst lengths supported
DDR SDRAM device attributes : # of banks on each DDR
SDRAM
DDR SDRAM device attributes : CAS Latency supported
D0
D3
128bytes
C0
C0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
256bytes
SDRAM DDR
13
9
1 Bank
64 bits
-
SSTL 2.5V
5ns
±0.65ns
5ns
±0.65ns
6ns
±0.70ns
50h
65h
08h
07h
0Dh
09h
01h
40h
00h
04h
50h
65h
00h
82h
10h
00h
01h
0Eh
04h
60h
70h
Non-parity, ECC
7.8us & Self refresh
x16
N/A
t
CCD
=1CLK
2,4,8
4 banks
18
2,2.5 (C0)
2,2.5,3 (D0/D3)
0CLK
1CLK
Differential clock /
non Registered
+/-0.2V voltage tolerance
5.0ns
±0.65ns
7.5ns
±0.75ns
15ns
6.0ns
±0.70ns
7.5ns
±0.75ns
15ns
7.5ns
±0.70ns
-
-
18ns
50h
65h
75h
75h
3Ch
0Ch
1Ch
01h
02h
20h
19
20
21
DDR SDRAM device attributes : CS Latency
DDR SDRAM device attributes : WE Latency
DDR SDRAM module attributes
22
23
24
25
26
27
DDR SDRAM device attributes : General
Min. Clock Cycle Time at second highest CL
Max. Data Access time from clock at second highest CL
Min. Clock Cycle Time at third highest CL
Max. Data Access Time from clock at third highest CL
Minimum row precharge time (=t
RP
)
00h
60h
70h
75h
75h
3Ch
75h
70h
00h
00h
48h
V826616B24SC Rev. 1.2 April 2006
5
FPGA/CPLD
