V826632G24SA
256 MB 200-PIN DDR UNBUFFERED SODIMM
32M x 64
Features
■
JEDEC 200 Pin DDR Unbuffered Small-Outline,
Dual In-Line memory module (SODIMM);
33,554,432 x 64 bit organization.
■
Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
■
Single +2.5V (± 0.2V) Power Supply
■
Single +2.6V (± 0.1V) Power Supply for DDR400
■
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■
Auto Refresh (CBR) and Self Refresh
■
All Inputs, Outputs are SSTL-2 Compatible
■
8192 Refresh Cycles every 64 ms
■
Serial Presence Detect (SPD)
■
Module Speed
t
CK
A1
t
AC
B0
B1
t
AC
C0
t
AC
Description
The V826632G24SA memory module is
organized 33,554,432 x 64 bits in a 200 pin memory
module. The 32M x 64 memory module uses 8
ProMOS 32M x 8 DDR SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
D4
D3
D0
C0
B1
B0
A1
Units
Clock Frequency
200
200
166
143
133
125
MHz
Module Speed
200
(PC400C) (PC400B) (PC400A) (PC333) (PC266A) (PC266B) (PC200)
(max.)
PC1600 (100MHz @ CL2)
Clock Cycle Time
7.5
7.5
7.5
7.5
10
10
ns
PC2100B (133MHz @ CL2.5) 7.5
CAS Latency = 2
PC2100A (133MHz @ CL2)
Clock Cycle Time
6
6
5
6
7
7.5
8
ns
PC2700 (166MHz @ CL2.5)
CAS Latency = 2.5
Clock Cycle Time
CAS Latency = 3
5
5
5
-
-
-
-
ns
t
RCD
tRP parameter
t
RP
tRCD parameter
4
4
3
3
3
3
3
3
2
2
3
3
2
2
CLK
CLK
V826632G24SA Rev. 1.1 February 2004
1
ProMOS TECHNOLOGIES
Part Number Information
V826632G24SA
V
ProMOS
8
2
6 6
DATA WIDTH
& COMP DENSITY
65 X64 using 128M
66 X64 using 256M
67 X64 using 512M
3 2
DATA
DEPTH
G
2
4
S
A
T
G
PCB TYPE
-
D
3
G : LEAD PLATING_GOLD
REFRESH
RATE
0: 4K
1: 2K
2: 8K
3: 1K
COMPONENT PKG
LEAD
LEAD
GREEN
PACKAGE
DESCRIPTION
I
J
M
TI
SI
TSOP
60-Ball FBGA
BGA
Die-Stacked TSOP
Die-Stacked FBGA
COMPONENT
REV LEVEL
L : LEAD PLATING_LOW PROFILE
W : LEAD FREE_GOLD
X : LEAD FREE_LOW PROFILE
Y : GREEN_GOLD
Z : GREEN_LOW PROFILE
TYPE
8
DDR
68 X64 using 1G
69 X64 using 2G
6A X64 using stacked 512M (256M die)
6B X64 using stacked 1G (256M die)
72 X72 using 64M
9 DDRII
BANKS
2 : 2 Banks
4 : 4 Banks
8 : 8 Banks
I/O INTERFACE
S: SSTL_2
Q: SSTL _18
PLATING FREE
T
S
B
TS
SS
E
F
H
TE
SF
VOLTAGE
2: 2.5 V
1: 1.8V
73 X72 using 128M
74 X72 using 512M
75 X72 using 512M
76 X72 using 1G
77 X72 using 2G
7A X72 using stacked 512M (256M die)
7B X72 using stacked 1G (256M die)
MODULE TYPE & COMP WIDTH
BASED ON
184PIN UNBUFFERED
184PIN REGISTERED
200PIN SODIMM
172PIN MicroDIMM
DDR2 UNBUFFERED
DDR2 REGISTERED
A4
C4
A6
C6
X4
I
N
V
X16
J
O
B
X8
K
U
G
M
A8
C8
SPEED
B0 :
B1 :
C0 :
D0 :
D1 :
D3 :
D4 :
PC2100B (133MHz @CL2.5-3-3)
PC2100A (133MHz @CL2-2-2)
PC2700 (166MHz @CL2.5-3-3)
PC3200 (200MHz @CL2.5-3-3)
PC3200 (200MHz @CL2-2-2)
PC3200 (200MHz @CL3-3-3)
PC3200 (200MHz @CL3-4-4)
V826632G24SA Rev. 1.1 February 2004
2
ProMOS TECHNOLOGIES
Block Diagram
CS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
V826632G24SA
D0
D4
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D1
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D5
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D2
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
Clock Wiring
Clock
Input
CK0/CK0
CK1/CK1
CK2/CK2
D6
SDRAMs
4 SDRAMs
4 SDRAMs
NC
Serial PD
SCL
WP
SDA
A0
SA0
A1
SA1
A2
SA2
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D3
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
DM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
D7
R=120
Ω
±
5%
Dram1
Dram2
Dram3
Dram4
Card
Edge
*Clock Net Wiring
BA0 - BA1
A0 - A12
RAS
CAS
CKE0
WE
BA0-BA1: DDR SDRAMs D0 - D7
V
DDSPD
SPD
D0 - D7
D0 - D7
A0-A12: DDR SDRAMs D0 - D7 V
DD
/V
DDQ
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
VREF
V
SS
V
DDID
D0 - D7
D0 - D7
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD
≠
VDDQ.
V826632G24SA Rev. 1.1 February 2004
3
ProMOS TECHNOLOGIES
Pin Configurations (Front Side/Back Side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
Front
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0
VSS
Key
V826632G24SA
Pin
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
Front
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2
VDD
CKE1
DU(A13)
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE
S0
DU
VSS
DQ32
DQ33
VDD
DQS4
Pin
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Front
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
DQ58
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
Back
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
Key
Pin
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
Back
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS
CAS
S1
DU
VSS
DQ36
DQ37
VDD
DM4
Pin
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
Notes:
*
These pins are not used in this module.
Pin Names
Pin
A0~A12
BA0~BA1
DQ0~DQ63
DQS0~DQS7
CK0~CK2, CK0~CK2,
CKE0
CS0
RAS
CAS
WE
DM0~DM7
Pin Description
Address Input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data - In Mask
Pin
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0~2
VDDID
NC
Pin Description
Power Supply 2.5V, DDR400 2.6V
Power Supply for DQS2.5V,
DDR400 2.6V
Ground
Power Supply for Reference
Serial EEPOM Power Supply (2.3V
to 3.6V)
Serial Data I/O
Serial Clock
Address in EEPROM
VDD Identification Flag
No Connection
V826632G24SA Rev. 1.1 February 2004
4
ProMOS TECHNOLOGIES
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
C0 (PC2700 @ CL2.5)
D0 (PC3200 @ 2.5-3-3)
D3 (PC3200 @ 3-3-3 )
D4 (PC3200 @ 3-4-4)
V826632G24SA
Byte
#
0
Function Supported
Function described
Defines # of Bytes written into serial memory at
module manufacturer
Total # of Bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module Rows on this assembly
Data width of this assembly
.........Data width of this assembly
VDDQ and interface standard of this assembly
Hex value
D4
A1
B0
B1
C0
80h
A1
B0
B1
C0
128bytes
D0
D3
D0
D3
D4
1
2
3
4
5
6
7
8
9
10
256bytes
SDRAM DDR
13
10
1 Bank
64 bits
-
SSTL 2.5V
6ns
5ns
5ns
5ns
08h
07h
0Dh
0Ah
01h
40h
00h
04h
80h 75h 70h 60h 50h 50h 50h
DDR SDRAM cycle time at highest CAS Latency 8ns 7.5ns 7ns
DDR SDRAM Access time from clock at highest ±0.8 ±0.75 ±0.75 ±0.70 ±0.65 ±0.65 ±0.65 80h 75h 75h 70h 65h 65h 65h
CL
ns
ns
ns
ns
ns
ns
ns
DIMM configuration type(Non-parity, Parity,
ECC)
Refresh rate & type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random
column
address
DDR SDRAM device attributes : Burst lengths
supported
DDR SDRAM device attributes : # of banks on
each DDR SDRAM
DDR SDRAM device attributes : CAS Latency
supported
DDR SDRAM device attributes : CS Latency
DDR SDRAM device attributes : WE Latency
DDR SDRAM module attributes
Non-parity, ECC
00h
11
12
13
14
15
7.8us & Self refresh
x8
N/A
t
CCD
=1CLK
82h
08h
00h
01h
16
2,4,8
0Eh
17
4 banks
04h
18
2,2.5,3
0Ch 0Ch 0Ch 0Ch 1Ch 1Ch 1Ch
19
20
21
0CLK
1CLK
Differential clock /
non Registered
+/-0.2V voltage tolerance
01h
02h
20h
22
23
DDR SDRAM device attributes : General
DDR SDRAM cycle time at second highest CL
00h
10ns 10ns 7.5ns 7.5ns 5.0ns 6.0ns 6.0ns A0h A0h 75h 75h 50h 60h 60h
V826632G24SA Rev. 1.1 February 2004
5
DIY/开源硬件专区
