V827432U24SA
2.5 VOLT 32M x 72 HIGH PERFORMANCE
LOW PROFILE (1U) REGISTERED ECC
DDR SDRAM MODULE
Features
■
184 Pin Registered 33,554,432 x 72 bit
Organization DDR SDRAM Modules
■
Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 and SOC Packages
■
Single +2.5V (± 0.2V) Power Supply
■
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■
Auto Refresh (CBR) and Self Refresh
■
All Inputs, Outputs are SSTL-2 Compatible
■
8192 Refresh Cycles every 64 ms
■
Serial Presence Detect (SPD)
■
1.2 or 1.125 inches Low Profile Registered
DIMM
Component
Used
-6
-7
Module Speed
t
CK
t
AC
Description
The V827432U24SA memory module is
organized 33,554,432 x 72 bits in a 184 pin memory
module. The 32M x 72 memory module uses 9
ProMOS 32M x 8 DDR SDRAM. The x72 low profile
modules are ideal for use in high performance
computer systems where increased memory
density, fast access times and small form factors
are required.
-75
-8
D0
(PC400A)
Units
D3
C0
166
(PC333)
B1
143
(PC266A)
B0
133
(PC266B)
Units
MHz
ns
ns
ns
CLK
CLK
Clock Frequency
166
143
133
125
MHz
Clock Frequency (max.)
(PC266A)(PC266B)
200
200
(PC333)
(max.)
(PC200)
(PC400B)
6
7
7.5
Clock Access
Clock Latency
Time CAS Cycle Time CAS Latency = 2
t
CK
= 2.5
Clock Cycle Time CAS Latency = 2.5
Clock Cycle Time CAS Latency = 3
8
7.5
5
5
3
3
ns
7.5
6
5
3
3
7.5
6
-
3
3
7.5
7
-
2
2
10
7.5
-
3
3
t
RCD
A1
t
RP
B0
B1
C0
Module
tRCD parameter
Speed
PC1600 (100MHz @ CL2)
tRP parameter
PC2100B (133MHz @ CL2.5)
PC2100A (133MHz @ CL2)
PC2700 (166MHz @ CL2.5)
V827432U24SA Rev. 1.2 April 2006
1
ProMOS TECHNOLOGIES
Part Number Information
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V827432U24SA
15
16
17
V
ProMOS
TYPE
8 : DDR
8
2
7 4
3 2
DATA
DEPTH
16 : 16Mb
32 : 32 Mb
64 : 64 Mb
65 : 128 Mb
66 : 256 Mb
U
2
REFRESH
RATE
0: 4K
2: 8K
4
S
A
COMPONENT
REV LEVEL
T
L
PCB TYPE
-
D
3
G : GOLD_LEAD PLATING
W : GOLD_RoHS
L : LOW PROFILE_LEAD PLATING
X : LOW PROFILE_RoHS
VOLTAGE
2 : 2.5V
DATA WIDTH
& COMP DENSITY
65
66
67
68
69
73
74
75
76
77
X64 using 128M
X64 using 256M
X64 using 512M
X64 using 1G
X64 using 2G
X72 using 128M
X72 using 256M
X72 using 512M
X72 using 1G
X72 using 2G
MODULE TYPE
& COMP WIDTH
BANKS
4 : 4 Banks
COMPONENT PKG
LEAD
PLATING
T
S
D
Z
I
J
N
P
GREEN
PACKAGE
DESCRIPTION
TSOP
FBGA
Die-stacked TSOP
Die-stacked FBGA
BASED ON
184PIN DIMM
UNBUFFERED
184PIN DIMM
REGISTERED
200PIN
SO-DIMM
172PIN
Micro-DIMM
X4 X16 X8
I
N
V
J
O
B
K
U
G
M
I/O INTERFACE
S: SSTL_2
SPEED
B0 : PC2100B (133MHz @CL2.5-3-3)
B1 : PC2100A (133MHz @CL2-2-2)
C0 : PC2700 (166MHz @CL2.5-3-3)
D0 : PC3200 (200MHz @CL2.5-3-3)
D3 : PC3200 (200MHz @CL3-3-3)
*RoHS: Restriction of Hazardous Substances
*GREEN: RoHS-compliant and Halogen-Free
Low Profile Module (1.2 in)
Register
PLL
SOC Based Low Profile Module (1.125 in)
This 256MB Registered ECC DDR DIMM is available in three different heights: 1.7", 1.2", and 1.125".
Please refer to pages 12 to 14 for the detailed mechanical diagrams of all three PCB heights.
V827432U24SA Rev. 1.2 April 2006
2
ProMOS TECHNOLOGIES
Block Diagram
RCS0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
V827432U24SA
DQS4
DM4/DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D0
D4
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D1
D5
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D2
D6
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D3
D7
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
V
DDSPD
V
DD
/V
DDQ
SPD
D0 - D8
D0 - D8
SCL
WP
Serial PD
SDA
A0
SA0
A1
SA1
A2
SA2
D8
VREF
V
SS
D0 - D8
D0 - D8
Strap: see Note 4
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
CS0
BA0-BAN
A0-A13
RAS
CAS
CKE0
WE
PCK
PCK
R
E
G
I
S
T
E
R
RCS0
RBA0 - RBAn
RA0 - RA12
RRAS
RCAS
RCKE0
RWE
RESET
BA0 -BAn : SDRAMs DQ0 - D8
A0 -An : SDRAMs D0 - D8
RAS: SDRAMs D0 - D8
CAS: SDRAMs D0 - D8
CKE : SDRAMs D0 - D8
WE SDRAMs D0 - D8
:
V827432U24SA Rev. 1.2 April 2006
3
ProMOS TECHNOLOGIES
Pin Configurations (Front Side/Back Side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Front
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
Vss
A1
CB0*
CB1*
VDD
DQS8*
A0
CB2*
VSS
CB3*
BA1
Key Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
A13*
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4*
CB5*
VDDQ
CK0*
CK0*
VSS
DM8*
A10
CB6*
VDDQ
CB7*
Key key
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
V827432U24SA
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Notes:
*
These pins are not used in this module.
Pin
Pin Description
Power Supply
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E
2
PROM Address Inputs
E
2
PROM Clock
E
2
PROM Data I/O
VDD Identification Flag
Do not Use
No Connection
Pin Names
Pin
CK1, CK1, CK2, CK2
CS0
CKE0
RAS, CAS, WE
A0 ~ A12
BA0, BA1
DQ0~DQ63
DQS0~DQS7
DM0~DM7
VDD
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
VDDID
DU
NC
V827432U24SA Rev. 1.2 April 2006
4
ProMOS TECHNOLOGIES
Serial Presence Detect Information
Bin Sort:
D0 (PC3200 @ CL 2.5-3-3)
D3 (PC3200 @ CL 3-3-3 )
C0 (PC2700 @ CL 2.5-3-3)
V827432U24SA
B1 (PC2100A @ CL 2-2-2)
B0 (PC2100B @ CL 2.5-3-3)
Byte
#
0
Function Supported
Function described
Defines # of Bytes written into serial memory at module
manufacturer
Total # of Bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module Rows on this assembly
Data width of this assembly
.........Data width of this assembly
VDDQ and interface standard of this assembly
DDR SDRAM cycle time at highest CAS Latency
DDR SDRAM Access time from clock at highest CL
DIMM configuration type(Non-parity, Parity, ECC)
Refresh rate & type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column
address
DDR SDRAM device attributes : Burst lengths support-
ed
DDR SDRAM device attributes : # of banks on each
DDR SDRAM
DDR SDRAM device attributes : CAS Latency support-
ed
DDR SDRAM device attributes : CS Latency
DDR SDRAM device attributes : WE Latency
DDR SDRAM module attributes
5ns
5ns
Hex value
B0
D0
D3
C0
80h
D0
D3
C0
128bytes
B1
B1
B0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
256bytes
SDRAM DDR
13
10
1 Bank
72 bits
-
SSTL 2.5V
6ns
7ns
7.5ns
50h 50h
08h
07h
0Dh
0Ah
01h
48h
00h
04h
60h
70h
02h
82h
08h
08h
01h
70h
75h
75h
75h
±0.65ns±0.65ns±0.70ns ±0.75ns ±0.75ns 65h 65h
Non-parity, ECC
7.8us & Self refresh
x8
x8
t
CCD
=1CLK
2,4,8
16
0Eh
17
4 banks
04h
18
2,2.5,3
1Ch 1Ch 0Ch 0Ch 0Ch
19
20
21
0CLK
1CLK
Registered address&
control inputs and On-card DLL
+/-0.2V voltage tolerance
5.0ns
6.0ns
7.5ns
7.5ns
10ns
50h 60h
01h
02h
26h
22
23
24
DDR SDRAM device attributes : General
DDR SDRAM cycle time at second highest CL
00h
75h
70h
75h A0h
75h
75h
DDR SDRAM Access time from clock at second highest ±0.65ns ±0.70ns ±0.70ns ±0.75ns ±0.75ns 65h 70h
CL
DDR SDRAM cycle time at third highest CL
7.5ns
7.5ns
-
-
-
75h 75h
25
00h
00h
00h
V827432U24SA Rev. 1.2 April 2006
5
