VA10800
VA10800 ARM
®
Cortex
®
-M0 MCU Datasheet
6.4.5
6.5
Input Leakage Current and
Output Voltage I2C Pads
...................... 24
.
DC Operating Current Consumption
25
Typical Operating Current
Table of Contents
1
Functional Description ....................... 3
1.1
Related Documentation
................... 3
1.2
Feature Summary ............................ 3
1.3
Power-Up Sequence ......................... 7
1.4
Power-Up and Reset Behavior of
pins
7
1.5
Other Resets .................................... 7
1.6
Support for in system programming
of the SPI ROM
............................................ 8
1.7
I
2
C pins ............................................. 8
Block Diagram
................................... 9
.
Pin Descriptions ............................... 10
Package Options .............................. 12
4.1
128 Pin Plastic LQFP
....................... 2
1
4.2
128 Pin Ceramic LQFP ....................
3
1
Die Options ...................................... 14
5.1
Table of Die Pad Coordinates from
Center of Die in Microns
............................ 4
1
5.2
Pad Layout with Marking in Upper
Left Corner of Die
...................................... 8
.
1
Ratings Tables ................................. 19
6.1
Absolute Maximum Ratings ..........
9
1
6.2
Recommended Supply Operating
Condition ....................................................
9
1
6.3
Recommended Supply Conditions
.. 9
1
6.4
Signal Pads Operating Conditions .
1
2
6.4.1
Non- I
2
C Pads
........................... 21
6.4.2
Leakage Current non-I2C pads
22
6.4.3
VOL, VOH non-I2C pads .......
23
6.4.4
I2C Pads
.................................... 23
6.5.1
6.6
6.7
6.8
Curves
26
DC Standby Current Consumption ..
7
2
Internal Weak Pull-up/Pull-down .
7
2
128 pin LQFP Pin Capacitance
........ 8
2
7
2
3
4
5
AC Electrical Characteristics ............. 29
7.1
AC Timing Conditions
...................... 9
2
7.1.1
Output delay derating for
loads
29
7.2
Internal Nominal 1 MHz Oscillator
29
7.3
Clock Signal .....................................
0
3
7.4
GPIO PORTA/PORTB .......................
0
3
2
7.5
I C pins ............................................
2
3
7.6
SPI ROM ..........................................
4
3
7.7
JTAG
................................................. 6
3
Package Mechanical Information ... 37
8.1
128 Pin Plastic LQFP Nominal
Package Dimensions (mm) .......................
7
3
8.2
128 Pin Ceramic LQFP Nominal
Package Dimensions (mm) .......................
8
3
Ordering Information ...................... 39
8
6
9
10 Development kit Ordering
Information
............................................. 39
11
12
Errata ............................................ 39
Revision History ........................... 40
www.voragotech.com
Rev 1.1
page 1
VA10800
VA10800
Features
§
§
Performance
o
50MHz ARM
®
Cortex
®
-M0 processor
On-Chip Memory
o
32KB Data
o
128KB Program
o
1Kb Efuse memory
56 General Purpose I/O (GPIO) pins
o
Configurable direction
o
Configurable weak pull-up/down
resistors
o
Configurable as edge or level
sensitive interrupt sources
24 General purpose counter/timers
o
Configurable interrupt sources
o
Can be triggered from 2 sources
(GPIO or other counter/timers)
2 UARTS
o
Internal FIFO
o
Transmit or receive interrupt source
2
½
Serial Peripheral Interface (SPI)
ports
o
Internal FIFO
o
Transmit or receive interrupt source
o
Multiple chip select outputs
o
Two ports Master/Slave, one port
Master only
2
2 I C ports
o
Internal FIFO
o
Master and Slave mode on both ports
o
Standard and Fast mode support
3.3V I/O Supply; 1.5V Core Supply
Description
The VA10800 ARM
®
Cortex
®
-M0
microcontroller chips using
HARDSlL
®
technology are designed for high reliability
applications. They have been designed for
extreme environment applications capable
of operating at extremely high and low
temperatures (-55˚C to 200˚C). These
devices are Latch up immune to the
extreme temperature specification of
200˚C.
The VA10800 is optimized for high
temperature environments and uses lower
power flip-flop storage elements.
§
§
§
§
§
§
www.voragotech.com
Rev 1.2
page 2
VA10800
VA10800
1 Functional Description
The VA10800 ARM
®
Cortex
®
-M0 microcontroller chip is designed for extreme temperature
applications. It is capable of operating at extremely high and low temperatures (-55˚C to
200˚C) and within extreme radiation environments. Lower power flip-flop storage elements
have been used in the design to optimize power consumption.
1.1 Related Documentation
The followed related documents will be helpful to fully understand this device:
•
ARM
®
Documents (Available from http://infocenter.arm.com)
o
o
o
o
•
Cortex
®
-M0 Generic User Guide
Cortex
®
-M0 Technical Reference Manual
AMBA
®
3 AHB-Lite Protocol Specification
AMBA
®
3 APB Protocol Specification
NXP Documents (Available from http://www.nxp.com)
o
I
2
C-bus specification and user manual
•
VORAGO Documents
o
VA10800/VA10820 Programmers Guide (Available at
http://voragotech.com)
1.2 Feature Summary
•
Processor Core
o
ARM
®
Cortex
®
-M0 processor
§
§
§
o
o
§
§
Up to 50 MHz
SysTick Counter
Single Cycle Multiply
32 Interrupts
4 Breakpoint Comparators
Rev 1.2
ARM
®
Cortex
®
-M0 built-in Nested Vectored Interrupt Controller (NVIC)
CoreSight™ compliant debug access via JTAG based Debug interface
www.voragotech.com
page 3
VA10800
VA10800
§
§
•
Memory
o
o
32kB Data Memory
128kB Code Memory
§
§
•
Peripherals
o
2 UARTs
§
§
16 word Transmit and Receive FIFOs
Fractional baud rate generation
•
§
§
§
§
§
Supports baud rates up to 115200 with system clocks above
2MHz
Supports 5, 6, 7, 8 and 9 bits
Supports Even, Odd, and None parity
Stop Bits 1 or 2
Supports Break generation and detection
Error detection
•
•
•
•
§
•
•
•
o
2
½
SPI Ports
§
§
§
§
§
§
§
Supports all 4 modes of Motorola’s SPI Specification
Word/Frame size of 4 to 16 bits
16 word Transmit and Receive FIFOs
Block mode support for larger Frame sizes
Master mode rates up to 1/4 the system clock
Slave mode rates up to 1/12 the system clock
Configurable Interrupt generation
Rev 1.2
FIFO overflow
Framing error
Parity error
Break detection
FIFO level (fully configurable)
Receive Timeout
Error
Loaded from external Serial Peripheral Interface (SPI) based memory at
startup
Configurable boot delay, boot speed, and boot checking
2 Data Watch Point Comparators
JTAG Debug Port
Configurable Interrupt generation
www.voragotech.com
page 4
VA10800
VA10800
•
•
•
§
§
o
I
2
C
§
§
§
§
§
§
o
GPIO
§
2 GPIO Ports, Up to 56 pins total
•
•
§
§
§
§
§
o
§
32 bit A port
24 bit B port
Standard I
2
C-compliant bus interface
Dedicated open-drain pins supporting I
2
C Fast-mode
Configurable as Master or Slave
16 word Transmit and Receive FIFOs
Configurable Interrupt generation
•
FIFO level (fully configurable)
Fast-Mode non-obstruct feature is not supported
FIFO level (fully configurable)
FIFO Overflow
Receive Timeout
2 Ports Configurable as Master or Slave
1 Port is Master Only
•
Uses the SPI Boot ROM pins after startup
Configurable direction control of individual bits
Bit level mask register allows single instruction setting or clearing of any
bits in one port.
Configurable interrupt detect on individual bits
•
Level or Edge sensitive
Configurable Pulse mode on individual bits
Configurable (0-3) cycle delay on individual bits
Manages GPIO/SPI/UART IO configurations:
•
•
•
•
Glitch filters
Pull-up/Pull-down
Signal inversion
Pseudo open-drain
IO Configuration
o
Counters/Timers
§
§
24 Counter/Timers
Advanced trigger modes
•
Start/Stop based on other Counter/Timers or GPIO signals
Rev 1.2
www.voragotech.com
page 5
