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VCC6-QCE-156M1734

LVPECL Output Clock Oscillator, 156.1734MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-6

器件类别：无源元件    振荡器   

厂商名称：Vectron International, Inc.

厂商官网：http://www.vectron.com/

器件标准：  

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参数 预览
器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Vectron International, Inc.
Reach Compliance Code
compliant
其他特性
ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TAPE AND REEL
最长下降时间
0.6 ns
频率调整-机械
NO
频率稳定性
25%
JESD-609代码
e4
制造商序列号
VCC6
安装特点
SURFACE MOUNT
标称工作频率
156.1734 MHz
最高工作温度
70 °C
最低工作温度
-10 °C
振荡器类型
LVPECL
输出负载
50 OHM
物理尺寸
7.0mm x 5.0mm x 1.6mm
最长上升时间
0.6 ns
最大供电电压
3.465 V
最小供电电压
3.135 V
标称供电电压
3.3 V
表面贴装
YES
最大对称度
55/45 %
端子面层
Gold (Au) - with Nickel (Ni) barrier
文档预览
VCC6
LVPECL, LVDS Crystal Oscillator Data Sheet
VCC6
Description
Vectron’s VCC6 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off either 2.5 or 3.3 volt supply,
hermetically sealed 5x7 ceramic package.
Features
•
•
•
•
•
•
•
Ultra Low Jitter Performance, Fundamental or 3rd OT Crystal Design
Output Frequencies to 350.000MHz
0.3 ps typical RMS jitter, 12k-20MHz
Differential Output
Enable/Disable
-10/70°C or -40/85°C Operation
Hermetically Sealed 5x7 Ceramic Package
•
•
•
•
•
•
•
•
•
•
Applications
Ethernet, GbE, Synchronous Ethernet
Fiber Channel
Enterprise Servers
Telecom
Clock source for A/D’s, D/A’s
Driving FPGA’s
Test and Measurement
PON
Medical
COTS
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
Complementary
Output
Output
V
DD
Crystal
Oscillator
E/D or NC
E/D or NC
Gnd
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page1
Performance Specifications
Table 1. Electrical Performance, LVPECL Option
Parameter
Voltage
1
Current (No Load)
Nominal Frequency
2
Stability
2,3
(Ordering Options)
Outputs
Output Logic Levels
4
, -10/70°C
Output Logic High
Output Logic Low
Output Logic Levels
4
, -40/85°C
Output Logic High
Output Logic Low
Output Rise and Fall Time
4
Load
Duty Cycle
5
Jitter (12 kHz - 20 MHz BW)155.52MHz
6
Period Jitter
7
RMS
P/P
Random Jitter
Deterministic Jitter
Output Enabled
8
Output Disabled
Enable/Disable Time
Enable/Disable Leakage Current
Enable Pull-Up Resistor
Output Enabled
Output Disabled
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
t
SU
T
OP
-10/70 or -40/85
5.0 x 7.0 x 1.8 or 5.08x7.5x2.2
33
1
10
фJ
фJ
2.3
20
2.4
0
Enable/Disable
V
IH
V
IL
t
D
0.7*V
DD
0.3*V
DD
200
±200
V
V
ns
uA
KOhm
MOhm
ms
°C
mm
ps
ps
ps
ps
45
V
OH
V
OL
V
OH
V
OL
t
R
/t
F
50 ohms into V
DD
-1.3V
50
0.3
55
0.7
%
ps
V
DD
-1.025
V
DD
-1.810
V
DD
-1.085
V
DD
-1.830
V
DD
-0.880
V
DD
-1.620
V
DD
-0.880
V
DD
-1.555
600
V
V
V
V
ps
Symbol
V
DD
I
DD
Min
Supply
3.135
2.375
Frequency
Typical
3.3
2.5
50
Maximum
3.465
2.625
98
350.000
Units
V
V
mA
MHz
ppm
f
N
10
±20, ±25, ±50, ±100
1. The VCC6 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. See Standard Frequencies and Ordering Information for more information.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Figure 1 defines the test circuit and Figure 2 defines these parameters.
5. Duty Cycle is defined as the On/Time Period.
6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VCC6 series”.
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
V
DD
-1.3V
t
R
t
F
1
NC
2
NC
3
6
5
4
50
50
V
OH
50%
V
OL
On Time
-1.3V
Period
Figure 1.
Figure 2.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page2
Performance Specifications
Table 2. Electrical Performance, LVDS Option
Parameter
Voltage
1
Current (No Load)
Nominal Frequency
2
Stability
2,3,
(Ordering Options)
Outputs
Output Logic Levels
4
Output Logic High
Output Logic Low
Differential Output
Differential Output Error
Offset Voltage
Offset Voltage Error
Output Leakage Current
Output Rise and Fall Time
4
Load
Duty Cycle
5
Jitter (12 kHz - 20 MHz BW)155.52MHz
6
Period Jitter
7
RMS
P/P
Random Jitter
Deterministic Jitter
Output Enabled
8
Output Disabled
Enable/Disable Time
Enable/Disable Leakage Current
Enable Pull-Up Resistor
Output Enabled
Output Disabled
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
t
SU
T
OP
-10/70 or -40/85
5.0 x 7.0 x 1.8 or 5.08x7.5x2.2
33
1
10
фJ
фJ
2.5
22
2.6
0
Enable/Disable
V
IH
V
IL
t
D
0.7*V
DD
0.3*V
DD
200
±200
V
V
ns
uA
KOhm
MOhm
ms
°C
mm
ps
ps
ps
ps
45
t
R
/t
F
100 ohms differential
50
0.3
55
0.7
%
ps
1.125
1.25
V
OH
V
OL
1.43
1.10
330
1.6
454
50
1.375
50
10
600
V
V
mV
mV
V
mV
uA
ps
Symbol
V
DD
I
DD
Min
Supply
3.135
2.375
Frequency
Typical
3.3
2.5
Maximum
3.465
2.625
60
Units
V
V
mA
MHz
ppm
f
N
10
±20, ±25, ±50, ±100
350.000
0.9
247
1. The VCC6 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. See Standard Frequencies and Ordering Information for more information.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Figure 2 defines these parameters and Figure 3 defines the test circuit.
5. Duty Cycle is defined as the On/Time Period.
6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VCC6 series”.
7. Measured using a LeCroy 8600, 25K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
50
50
Out
Out
0.01 uF
DC
6
1
5
2
4
3
Figure 3.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page3
Package and Pinout
Table 3. Pinout
Pin #
1
2
3
4
5
6
Symbol
E/D or NC
E/D or NC
GND
f
O
Cf
O
V
DD
Function
Enable Disable or No Connection
Enable Disable or No Connection
Electrical and Lid Ground
Output Frequency
Complementary Output Frequency
Supply Voltage
The Enable/Disable function is set at the factory on either pin 1
or pin 2 and is an ordering option
6
7.0±0.15
5
Part Number
Frequency
Date Code
4
6
7.49±0.15
5
Part Number
Frequency
Date Code
4
5.0±0.15
5.08±0.15
1
2
1.397
3
1.6 max
1.27
1
2
1.397
3
2.16 max
1.27
1
6
2
Bottom View
5
3
3.57
4
Dimensions are in mm
1
6
2
Bottom View
5
3
3.57
4
2.54
5.08
5.08
2.54
Figure 4. Package A Outline Drawing
Figure 5. Optional Package Outline Drawing
The VCC6 can be supplied in one of two package options and
Figure 4 shows the primary package used. The pad layout and
dimesnions are identical and a reel would include only 1 of the
two options
1.78
1.96
3.66
2.54
5.08
Figure 6. Pad Layout
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page4
LVPECL Application Diagrams
Figure 7. Standard PECL Output Configuration Figure 8. Single Resistor Termination Scheme
Resistor values are typically 120 to 240 ohms
for 3.3V operation.
Resistor values are typically 82 to 120 ohms
for 2.5V operation.
Figure 9. Pull-Up Pull Down Termination
Resistor values are typically for 3.3V operation
For 2.5V operation, the resistor to ground is 62
ohms and the resistor to supply is 240 ohms
The VCC6 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 7. There are numerous application notes on
terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 8, and a pull-up/pull-down scheme as
shown in Figure 9. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
LVDS Application Diagrams
V
CC
LVDS
Driver
100
LVDS
Receiver
LVDS
Driver
100
Receiver
OUT+
OUT-
Figure 10 Standard LVDS
Output Configuration
Figure 11. LVDS to LVDS Connection, Internal 100ohm
Figure 12. LVDS to LVDS Connection
Some LVDS structures have an internal 100 ohm resistor on the
External 100ohm and AC blocking caps
input and do not need additional components.
Some input structures may not have an internal 100 ohm
resistor on the input and will need an external 100ohm
resistor for impedance matching. Also, the input may have
an internal DC bias which may not be compatible with
LVDS levels, AC blocking capacitors can be used.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Environmental and IR Compliance
Table 4. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Fine and
Gross Leak
Resistance to Solvents
Moisture Sensitivity Level
Contact Pads
Condition
MIL-STD-883 Method 2002
MIL-STD-883 Method 2007
MIL-STD-883 Method 1010
MIL-STD-883 Method 2003
MIL-STD-883 Method 1014
MIL-STD-883 Method 2015
MSL1
Gold over Nickel
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page5
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器件捷径:
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