PRELIMINARY DATA SHEET
MICRONAS
VCT 38xxA/B
Video/Controller/Teletext
IC Family
Edition Jan. 8, 2002
6251-518-1PD
MICRONAS
VCT 38xxA/B
Contents
Page
Section
Title
PRELIMINARY DATA SHEET
7
8
8
8
8
8
8
8
1.
1.1.
1.1.1.
1.1.2.
1.1.3.
1.1.4.
1.1.5.
1.1.6.
Introduction
Features
Video Features
Microcontroller Features
OSD Features
Teletext Features
Audio Features
General Features
9
10
1.2.
1.3.
Chip Architecture
System Application
11
11
11
11
11
11
11
12
12
2.
2.1.
2.2.
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.2.6.
Video Processing
Introduction
Video Front-end
Input Selector
Clamping
Automatic Gain Control
Analog-to-Digital Converters
Digitally Controlled Clock Oscillator
Analog Video Output
12
13
13
14
14
14
14
15
15
16
16
2.3.
2.4.
2.4.1.
2.4.2.
2.4.3.
2.4.4.
2.4.5.
2.4.6.
2.4.7.
2.4.8.
2.4.9.
Adaptive Comb Filter
Color Decoder
IF-Compensation
Demodulator
Chrominance Filter
Burst Detection / Saturation Control
Color Killer Operation
Automatic Standard Recognition
PAL Compensation/1-H Comb Filter
Luminance Notch Filter
Skew Filtering
16
17
17
17
18
18
18
19
20
20
20
20
21
21
21
21
22
22
22
2.5.
2.6.
2.7.
2.8.
2.9.
2.9.1.
2.9.2.
2.9.3.
2.9.4.
2.9.5.
2.9.6.
2.9.7.
2.9.8.
2.9.9.
2.9.10.
2.9.11.
2.9.12.
2.9.13.
2.9.14.
Horizontal Scaler
Black-line Detector
Test Pattern Generator
Video Sync Processing
Display Processing
Luma Contrast Adjustment
Black-Level Expander
Dynamic Peaking
Digital Brightness Adjustment
Soft Limiter
Chroma Interpolation
Chroma Transient Improvement
Inverse Matrix
RGB Processing
OSD Color Look-up Table
Picture Frame Generator
Priority Decoder
Scan Velocity Modulation
Display Phase Shifter
24
24
25
26
26
26
2.10.
2.10.1.
2.10.2.
2.10.3.
2.10.4.
2.10.5.
Video Back-end
CRT Measurement and Control
SCART Output Signal
Average Beam Current Limiter
Analog RGB Insertion
Fast-Blank Monitor
2
Micronas
PRELIMINARY DATA SHEET
VCT 38xxA/B
Contents, continued
Page
28
28
28
28
29
29
30
Section
2.11.
2.11.1.
2.11.2.
2.11.3.
2.11.4.
2.11.5.
2.11.6.
Title
Synchronization and Deflection
Deflection Processing
Angle and Bow Correction
Horizontal Phase Adjustment
Vertical and East/West Deflection
EHT Compensation
Protection Circuitry
30
30
31
31
44
46
2.12.
2.13.
2.14.
2.14.1.
2.14.1.1.
2.14.1.2.
Reset Function
Standby and Power-On
I
2
C Bus Slave Interface
Control and Status Registers
Scaler Adjustment
Calculation of Vertical and East-West Deflection Coefficients
48
48
48
48
50
50
50
51
51
53
54
3.
3.1.
3.2.
3.3.
3.4.
3.5.
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
Text and OSD Processing
Introduction
SRAM Interface
Text Controller
Teletext Acquisition
Teletext Page Management
Memory Manager
Memory Organization
Page Table
Ghost Row Organization
Subpage Manager
55
56
58
59
60
61
62
63
64
65
3.6.
3.7.
3.8.
3.8.1.
3.8.2.
3.8.3.
3.8.4.
3.8.5.
3.8.6.
3.8.7.
WST Display Controller
Display Memory
Character Generator
Character Code Mapping
Character Font ROM
Latin Font Mapping
Cyrillic Font Mapping
Arabic Font Mapping
Closed Caption Font (on VCT 38xxB only!)
Character Font Structure
66
68
69
70
78
85
85
86
86
86
87
87
3.9.
3.10.
3.11.
3.12.
3.13.
3.14.
3.14.1.
3.14.1.1.
3.14.1.2.
3.14.1.3.
3.14.1.4.
3.14.1.5.
National Character Mapping
Four-Color Mode
OSD Layer
Command Language
I/O Register
I
2
C-Bus Slave Interface
Subaddressing
CPU Subaddressing
DRAM Subaddressing
Command Subaddressing
Data Subaddressing
Hardware Identification
Micronas
3
VCT 38xxA/B
Contents, continued
Page
Section
Title
PRELIMINARY DATA SHEET
88
88
88
88
88
4.
4.1.
4.2.
4.3.
4.4.
Audio Processing
Introduction
Input Select
Volume Control
I
2
C-Bus Slave Interface
89
89
89
89
5.
5.1.
5.2.
5.2.1.
TV Controller
Introduction
CPU
CPU Slow Mode
90
90
90
5.3.
5.3.1.
5.3.2.
RAM and ROM
Address Map
Bootloader
91
93
94
95
95
95
95
95
96
96
96
97
98
98
98
5.4.
5.5.
5.6.
5.7.
5.7.1.
5.7.2.
5.7.2.1.
5.7.2.2.
5.7.3.
5.7.3.1.
5.7.3.2.
5.7.3.3.
5.7.4.
5.7.5.
5.7.6.
Control Register
Standby Registers
Test Registers
Reset Logic
Alarm Function
Software Reset
From Standby into Normal Mode
From Normal into Standby Mode
Internal Reset Sources
Supply Supervision
Clock Supervision
Watchdog
External Reset Sources
Summary of Module Reset States
Reset Registers
99
99
5.8.
5.8.1.
Memory Banking
Banking Register
101
103
5.9.
5.9.1.
DMA Interface
DMA Registers
104
104
104
104
104
104
106
107
109
109
111
113
5.10.
5.10.1.
5.10.2.
5.10.3.
5.10.4.
5.10.5.
5.10.6.
5.10.7.
5.10.8.
5.10.8.1.
5.10.9.
5.10.10.
Interrupt Controller
Features
General
Initialization
Operation
Inactivation
Precautions
Interrupt Registers
Interrupt Assignment
Interrupt Multiplexer
Port Interrupt Module
Interrupt Timing
114
114
114
114
115
115
5.11.
5.11.1.
5.11.2.
5.11.3.
5.11.4.
5.11.5.
Memory Patch Module
Features
General
Initialization
Patch Operation
Patch Registers
I
2
C Bus Master Interface Registers
116
118
5.12.
5.12.1.
I
2
C-Bus Master Interface
120
120
120
121
5.13.
5.13.1.
5.13.2.
5.13.3.
Timer T0 and T1
Features
Operation
Timer Registers
4
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PRELIMINARY DATA SHEET
VCT 38xxA/B
Contents, continued
Page
122
122
123
123
123
123
124
124
124
125
Section
5.14.
5.14.1.
5.14.2.
5.14.3.
5.14.3.1.
5.14.3.2.
5.14.3.3.
5.14.3.4.
5.14.4.
5.14.5.
Title
Capture Compare Module (CAPCOM)
Features
Initialization
Operation of CCC
Operation of Subunit
Compare and Output Action
Capture and Input Action
Interrupts
Inactivation
CAPCOM Registers
127
127
127
127
127
127
5.15.
5.15.1.
5.15.2.
5.15.3.
5.15.4.
5.15.5.
Pulse Width Modulator
Features
General
Initialization
Operation
PWM Registers
128
128
128
129
129
129
5.16.
5.16.1.
5.16.2.
5.16.3.
5.16.4.
5.16.5.
Tuning Voltage Pulse Width Modulator
Features
General
Initialization
Operation
TVPWM Registers
130
130
131
131
131
132
5.17.
5.17.1.
5.17.2.
5.17.3.
5.17.4.
5.17.5.
A/D Converter (ADC)
Features
Operation
Measurement Errors
Comparator
ADC Registers
133
133
134
134
134
134
134
134
134
134
134
135
5.18.
5.18.1.
5.18.2.
5.18.2.1.
5.18.2.2.
5.18.2.3.
5.18.2.4.
5.18.2.5.
5.18.2.6.
5.18.2.7.
5.18.2.8.
5.18.3.
Closed Caption Module (CC)
Features
Operation
Lowpass filter
Input timing
Threshold adaption
Bitslicing
Timing recovery
Shift register
Controlling
Formatter
CCM Registers
137
137
138
138
139
139
140
140
141
141
142
142
5.19.
5.19.1.
5.19.2.
5.19.2.1.
5.19.2.2.
5.19.3.
5.19.4.
5.19.4.1.
5.19.5.
5.19.5.1.
5.19.6.
5.19.6.1.
Ports
Port Assignment
Universal Ports P1 to P3
Features
Universal Port Mode
Universal Port Registers
I
2
C Ports P40 and P41
Features
Audio Ports P42 to P46
Features
CLK20 Output Port
Features
143
5.20.
I/O Register Cross Reference
Micronas
5
编程基础
