ADVANCE INFORMATION
MICRONAS
VCT 38xxA
Video/Controller/Teletext
IC Family
Edition Oct. 17, 2000
6251-518-1AI
MICRONAS
VCT 38xxA
Contents
Page
Section
Title
ADVANCE INFORMATION
7
8
8
8
8
8
8
8
1.
1.1.
1.1.1.
1.1.2.
1.1.3.
1.1.4.
1.1.5.
1.1.6.
Introduction
Features
Video Features
Microcontroller Features
OSD Features
Teletext Features
Audio Features
General Features
9
10
1.2.
1.3.
Chip Architecture
System Application
11
11
11
11
11
11
11
12
12
2.
2.1.
2.2.
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.2.6.
Video Processing
Introduction
Video Front-end
Input Selector
Clamping
Automatic Gain Control
Analog-to-Digital Converters
Digitally Controlled Clock Oscillator
Analog Video Output
12
13
13
14
14
14
14
14
15
15
16
16
2.3.
2.4.
2.4.1.
2.4.2.
2.4.3.
2.4.4.
2.4.5.
2.4.6.
2.4.7.
2.4.8.
2.4.9.
2.4.10.
Adaptive Comb Filter
Color Decoder
IF-Compensation
Demodulator
Chrominance Filter
Frequency Demodulator
Burst Detection / Saturation Control
Color Killer Operation
Automatic Standard Recognition
PAL Compensation/ 1-H Comb Filter
Luminance Notch Filter
Skew Filtering
16
16
17
17
18
18
18
18
19
21
21
21
21
22
22
22
22
23
23
23
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
2.10.1.
2.10.2.
2.10.3.
2.10.4.
2.10.5.
2.10.6.
2.10.7.
2.10.8.
2.10.9.
2.10.10.
2.10.11.
2.10.12.
2.10.13.
2.10.14.
Horizontal Scaler
Black-line Detector
Test Pattern Generator
Video Sync Processing
Macrovision Detection
Display Processing
Luma Contrast Adjustment
Black-Level Expander
Dynamic Peaking
Digital Brightness Adjustment
Soft Limiter
Chroma Interpolation
Chroma Transient Improvement
Inverse Matrix
RGB Processing
OSD Color Look-up Table
Picture Frame Generator
Priority Decoder
Scan Velocity Modulation
Display Phase Shifter
2
Micronas
ADVANCE INFORMATION
VCT 38xxA
Contents, continued
Page
25
25
26
27
27
27
Section
2.11.
2.11.1.
2.11.2.
2.11.3.
2.11.4.
2.11.5.
Title
Video Back-end
CRT Measurement and Control
SCART Output Signal
Average Beam Current Limiter
Analog RGB Insertion
Fast-Blank Monitor
29
29
29
29
30
30
31
2.12.
2.12.1.
2.12.2.
2.12.3.
2.12.4.
2.12.5.
2.12.6.
Synchronization and Deflection
Deflection Processing
Angle and Bow Correction
Horizontal Phase Adjustment
Vertical and East/West Deflection
EHT Compensation
Protection Circuitry
31
31
32
32
44
46
2.13.
2.14.
2.15.
2.15.1.
2.15.1.1.
2.15.1.2.
Reset Function
Standby and Power-On
I
2
C Bus Slave Interface
Control and Status Registers
Scaler Adjustment
Calculation of Vertical and East-West Deflection Coefficients
47
47
47
47
49
49
49
50
50
52
52
3.
3.1.
3.2.
3.3.
3.4.
3.5.
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
Text and OSD Processing
Introduction
SRAM Interface
Text Controller
Teletext Acquisition
Teletext Page Management
Memory Manager
Memory Organization
Page Table
Ghost Row Organization
Subpage Manager
53
55
57
58
59
60
61
62
63
3.6.
3.7.
3.8.
3.8.1.
3.8.2.
3.8.3.
3.8.4.
3.8.5.
3.8.6.
WST Display Controller
Display Memory
Character Generator
Character Code Mapping
Character Font ROM
Latin Font Mapping
Cyrillic Font Mapping
Arabic Font Mapping
Character Font Structure
64
66
67
68
76
82
82
82
83
83
83
84
3.9.
3.10.
3.11.
3.12.
3.13.
3.14.
3.14.1.
3.14.1.1.
3.14.1.2.
3.14.1.3.
3.14.1.4.
3.14.1.5.
National Character Mapping
Four-Color Mode
OSD Layer
Command Language
I/O Register
I
2
C-Bus Slave Interface
Subaddressing
CPU Subaddressing
DRAM Subaddressing
Command Subaddressing
Data Subaddressing
Hardware Identification
Micronas
3
VCT 38xxA
Contents, continued
Page
Section
Title
ADVANCE INFORMATION
85
85
85
85
85
4.
4.1.
4.2.
4.3.
4.4.
Audio Processing
Introduction
Input Select
Volume Control
I
2
C-Bus Slave Interface
86
86
86
86
5.
5.1.
5.2.
5.2.1.
TV Controller
Introduction
CPU
CPU Slow Mode
87
87
87
5.3.
5.3.1.
5.3.2.
RAM and ROM
Address Map
Bootloader
87
89
90
90
90
90
91
91
91
92
92
93
94
94
94
5.4.
5.5.
5.6.
5.7.
5.7.1.
5.7.2.
5.7.2.1.
5.7.2.2.
5.7.3.
5.7.3.1.
5.7.3.2.
5.7.3.3.
5.7.4.
5.7.5.
5.7.6.
Control Register
Standby Registers
Test Registers
Reset Logic
Alarm Function
Software Reset
From Standby into Normal Mode
From Normal into Standby Mode
Internal Reset Sources
Supply Supervision
Clock Supervision
Watchdog
External Reset Sources
Summary of Module Reset States
Reset Registers
95
95
5.8.
5.8.1.
Memory Banking
Banking Register
96
98
5.9.
5.9.1.
DMA Interface
DMA Registers
99
99
99
99
99
99
101
101
103
103
104
106
5.10.
5.10.1.
5.10.2.
5.10.3.
5.10.4.
5.10.5.
5.10.6.
5.10.7.
5.10.8.
5.10.8.1.
5.10.9.
5.10.10.
Interrupt Controller
Features
General
Initialization
Operation
Inactivation
Precautions
Interrupt Registers
Interrupt Assignment
Interrupt Multiplexer
Port Interrupt Module
Interrupt Timing
107
107
107
107
108
108
5.11.
5.11.1.
5.11.2.
5.11.3.
5.11.4.
5.11.5.
Memory Patch Module
Features
General
Initialization
Patch Operation
Patch Registers
109
111
5.12.
5.12.1.
I
2
C-Bus Master Interface
I2C Bus Master Interface Registers
4
Micronas
ADVANCE INFORMATION
VCT 38xxA
Contents, continued
Page
113
113
113
114
Section
5.13.
5.13.1.
5.13.2.
5.13.3.
Title
Timer T0 and T1
Features
Operation
Timer Registers
115
115
116
116
116
117
118
5.14.
5.14.1.
5.14.2.
5.14.3.
5.14.3.1.
5.14.4.
5.14.5.
Capture Compare Module (CAPCOM)
Features
Initialization
Operation of CCC
Operation of Subunit
Inactivation
CAPCOM Registers
120
120
120
120
120
120
5.15.
5.15.1.
5.15.2.
5.15.3.
5.15.4.
5.15.5.
Pulse Width Modulator
Features
General
Initialization
Operation
PWM Registers
121
121
121
122
122
122
5.16.
5.16.1.
5.16.2.
5.16.3.
5.16.4.
5.16.5.
Tuning Voltage Pulse Width Modulator
Features
General
Initialization
Operation
TVPWM Registers
123
123
123
124
124
125
5.17.
5.17.1.
5.17.2.
5.17.3.
5.17.4.
5.17.5.
A/D Converter (ADC)
Features
Operation
Measurement Errors
Comparator
ADC Registers
126
126
127
127
128
128
129
129
130
130
131
131
5.18.
5.18.1.
5.18.2.
5.18.2.1.
5.18.2.2.
5.18.3.
5.18.4.
5.18.4.1.
5.18.5.
5.18.5.1.
5.18.6.
5.18.6.1.
Ports
Port Assignment
Universal Ports P1 to P3
Features
Universal Port Mode
Universal Port Registers
I
2
C Ports P40 and P41
Features
Audio Ports P42 to P46
Features
CLK20 Output Port
Features
132
5.19.
I/O Register Cross Reference
Micronas
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