VIS
Description
VG36644041BT / VG36648041BT / VG36641641BT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 4,194,304 words x 4 bits x 4 banks,
2,097,152 words x 8 bits x 4 banks and 1,048,576 words x 16 bits x 4 banks, respectively. It is fabricated with
an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It
is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V (
±
0.3V ) power supply
• High speed clock cycle time : 6 / 7 / 8 only for x16 organization
7L / 8H only for x4 / x8 organization
PC100(8H), PC133(7L)
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2, 3)
• Programmable burst length (1, 2, 4, 8 & Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A12 & A13 (Bank Select)
• Each Bank can operate simultaneously and independently
• LVTTL compatible I/O interface
• Random column access in every cycle
• X4 / X8 / X16 organization
• Input/Output controlled by DQM(X4 / X8) ,LDQM and UDQM(X16)
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
Document :1G5-0152
Rev.3
Page 1
VIS
P
in Configuration
VG36644041BT / VG36648041BT / VG36641641BT
CMOS Synchronous Dynamic RAM
VG36644041 ( x4 )
VG36648041 ( x8 )
VG36641641 ( x16 )
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
DD
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
DD
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
DD
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Description
VG36644041B / VG36648041B / VG36641641B
Pin Name
Function
A
0
- A
11
A13/BA0,
A12/BA1
DQ
0
~ DQ
15
RAS
CAS
WE
V
SS
V
DD
Address inputs
Bank select
Data - in/data - out
Row address strobe
Column address strobe
Write enable
Ground
Power (+ 3.3V)
Pin Name
DQM
LDQM
UDQM
CLK
CKE
CS
V
DDQ
V
SSQ
Function
DQ Mask enable
Upper DQ Mask enable
Lower DQ Mask enable
Clock input
Clock enable
Chip select
Supply voltage for DQ
Ground for DQ
Document :1G5-0152
Rev.3
Page 2
VIS
Block Diagram
CLK
CKE
Clock
Generator
VG36644041BT / VG36648041BT / VG36641641BT
CMOS Synchronous Dynamic RAM
Address
Mode
Register
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Command Decoder
Sense Amplifier
Control Logic
Column
Address
Buffer
&
Burst
Counter
Column Decoder &
Latch Circuit
Input & Output
Buffer
Latch Circuit
CS
RAS
CAS
WE
DQM
Data Control Circuit
DQ
Document :1G5-0152
Rev.3
Page 3
VIS
Absolute Maximum D.C. Ratings
Parameter
Voltage on any pin relative to Vss
Supply voltage relative to Vss
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
VG36644041BT / VG36648041BT / VG36641641BT
CMOS Synchronous Dynamic RAM
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
I
OUT
P
D
T
OPT
T
STG
Value
-0.5 to + 4.6
-0.5 to + 4.6
50
1.0
0 to +70
-55 to +125
Unit
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
peumanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Maximum A.C. Operating Requirements for LVTTL Compatible
Parameter
Input High Voltage
Input Low Voltage
Symbol
V
IH
V
IL
Min
2.0
V
SSQ
- 2.0
Max
V
DDQ
+ 2.0
0.8
Unit
V
V
Notes
2
2
Recommended DC Operating Conditions for LVTTL Compatible
Parameter
Supply Voltage
Input High Voltage, all inputs
Input Low Voltage, all inputs
Symbol
V
DD,
V
DDQ
V
IH
V
IL
Min
3.0
2.0
-0.3
Typ
3.3
-
-
Max
3.6
V
DD
+ 0.3
0.8
Unit
V
V
V
Capacitance
(Ta = 25°C, f = 1MHZ)
Parameter
Input capacitance (all input pins except CLK pin)
Input capacitance (CLK pin)
Data input/output capacitance
Symbol
C
in
C
CLK
C
I/O
Min
2.5
2.5
4.0
Typ
3.75
3.25
5.25
Max
5.0
4.0
6.5
Unit
pF
pF
pF
Notes
1
1
1
Notes : 1. Capacitance measured with effective capacitance measuring method.
2. The overshoot and undershoot voltage duration is
≤
3ns with no input clamp diodes.
Document :1G5-0152
Rev.3
Page 4
VIS
VG36644041BT / VG36648041BT / VG36641641BT
CMOS Synchronous Dynamic RAM
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
, for x4 / x8 Configuration
VG36644041B / VG36648041B
Parameter
Symbol
Test Conditions
-7L
-8H
Unit Notes
Min
Max
Min
Max
CL = 3
120
95
mA
1
Operating current
I
CC1
Burst length = 1
One bank active
CL = 2
120
95
t
RC
≤
t
RC(MIN)
, Io = 0mA
Precharge standby
I
CC2P
current in power
I
CC2PS
down mode
Precharge standby current in I
CC2N
Nonpower down mode
CKE
CKE
≤
V
IL(MAX)
t
CK
= 10ns
2
2
25
2
2
25
mA
≤
V
IL(MAX)
t
CK
=
∞
CKE
CKE
≥
V
IH(MIN)
t
CK
= 10ns.
CKE
≥
V
IH(MIN)
CS
Input signals are changed one time
during 2 CLK cycles.
mA
I
CC2NS
CKE
≥
V
CKE
V
IH(MIN)
, t
CK
=
CLK
≤
V
IL(MAX)
Input signals are stable.
CKE
CKE
∞
20
20
Active standby current in
power down mode
Active standby current in
Nonpower down mode
I
CC3P
I
CC3PS
I
CC3N
≤
V
IL(MAX)
, t
CK
= 10ns
7
5
55
7
5
55
mA
≤
V
IL(MAX)
, t
CK
=
∞
CKE
≥
V
IH(MIN)
, t
CK
= 10ns
CKE
CS
CKE
≥
V
IH(MIN)
Input signals are changed
one time during 2CLKs.
CKE
≥
V
IH(MIN)
t
CK
=
CKE
mA
I
CC3NS
CLK
≤
V
IL(MAX)
Input signals are stable.
Operating current
(Burst mode)
Refresh current
Self refresh current
Input leakage current
(Inputs)
Input leakage current
(I/O pins)
Output Low Voltage
Output High Voltage
I
CC4
I
CC5
I
CC6
I
IL
I
IL
V
OL
V
OH
t
CK
CKE
t
RC
All banks Active
∞
40
40
t
CK(MIN)
, Io = 0mA
≥
V
CL = 3
CL = 2
170
170
170
1
2
1
1.5
0.4
2.4
2.4
140
140
160
1
2
1
1.5
0.4
mA
mA
mA
mA
µA
µA
V
V
2
3
4
≥
t
RC(MIN)
CKE
≤
0.2V
0
≤
V
IN
≤
V
DD(MAX)
Pins not under test = 0V
0
≤
V
OUT
≤
V
DD(MAX)
DQ# in H - Z., Dout disabled
I
OL
= 2mA
I
OH
= -2mA
-1
-1.5
-1
-1.5
5
5
Notes:
1. I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, I
CC1
is measured on condition that addresses are changed only one
time during t
CK(MIN)
.
2. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, I
CC4
is measured on condition that addresses are changed only one
time during t
CK(MIN.)
.
3. I
CC5
is measured on condition that addresses are changed only one time during t
CK(MIN)
.
4. S Version
5. For LVTTL compatible.
Document :1G5-0152
Rev.3
Page 5
