®
VK05CFL
ELECTRONIC DRIVER FOR CFL APPLICATION
TYPE
VK05CFL
B
V
520 V
I
Crms
0.25A
I
Peak
1.5A
EMITTER SWITCH POWER OUTPUT STAGE
s
INTEGRATED ANTIPARALLEL COLLECTOR
SOURCE DIODE
s
INTEGRATED DIAC FUNCTION
s
NOMINAL WORKING FREQUENCY
SETTABLE BY EXTERNAL CAPACITOR
s
IGNITION FREQUENCY SET BY LOAD
s
SO-8
DESCRIPTION
The VK05CFL is a monolithic device housed in a
standard SO-8 package, made by using
STMicroelectronics proprietary VIPower M3
Technology. This device is intended both for the
low side and the high side driver in half bridge CFL
applications. This means that it is possible to
realize a complete H-bridge by using two
VK05CFL devices: one connected in HSD
configuration and the other connected in LSD
configuration. In the VK05CFL used in HSD
BLOCK DIAGRAM
configuration, the diac pin must be connected to
source pin. Both diac functionality and discharge
circuit for external diac capacitor are integrated.
By an external capacitor it is possible to choose
the nominal working frequency without influence
on the ignition one.
Collector
diac
Diac
sec
osc
R
5Vref
2Vref
+
-
-
+
Source
September 2002
1/14
VK05CFL
ABSOLUTE MAXIMUM RATING
Symbol
V
CS
I
sec
V
sec
I
CM
I
OSC
V
OSC
T
j
T
stg
Parameter
Collector-Source Voltage
Input Current (secondary)
Input Voltage (secondary)
Collector Peak Current
Osc Pin Current
Osc Pin Voltage
Max Operating Junction Temperature
Storage Temperature Range
Max
520
-100
140
Internally limited
-1.8
1.8
100
Internally limited
-40
150
-55
150
Min
Typ
Unit
V
mA
V
A
mA
V
°C
°C
THERMAL DATA
Symbol
R
thj-lead
R
thj-amb
Parameter
Thermal Resistance Junction - lead
Thermal Resistance Junction - ambient
Max
Max
Value
15
52 (*)
Unit
°C/W
°C/W
(*) When mounted on a standard single-sided FR-4 board with 100mm
2
of Cu (at least 35µm thick).
CONNECTION DIAGRAM
Collector
Collector
Collector
Collector
5
4
8
1
sec
osc
diac
Source
SO-8
PIN FUNCTIONS
Pin Name
Collector
Source
diac
sec
osc
Pin Function
Collector of the NPN high voltage transistor in the cascode configuration.
Low voltage Power MOSFET source in the cascode configuration and GROUND reference.
Input of the diac block to start the system up at the beginning.
Connection with secondary winding of the voltage transformer, in order to trigger and to supply the
device.
Output via to charge external capacitor necessary to set the steady state working frequency.
2/14
VK05CFL
ELECTRICAL CHARACTERISTICS
(T
case
=25°C unless otherwise specified)
FORWARD
Symbol
V
CS(sat)
Parameter
Test Conditions
Collector-Source Saturation Voltage V
sec
=10V; I
C
=300mA
Min
Typ
1.4
Max
2.8
Unit
V
REVERSE
Symbol
V
CSr
Parameter
Collector-Source Reverse Voltage
Test Conditions
I
C
= -300mA
Min
Typ
-1
Max
-1.5
Unit
V
OSC
Symbol
I
OSC
V
OSC(th)
Parameter
Osc Output Current
Osc Turn-off Voltage
Test Conditions
V
sec
=10V; V
OSC
=0V
V
sec
=10V
Min
Typ
300
1.6
Max
2
Unit
µ
A
V
DIAC
Symbol
V
diac(thH)
V
diac(thL)
Parameter
Diac On Threshold
Diac Off Threshold
Test Conditions
Min
28
18
Typ
31
Max
35
Unit
V
V
SEC
Symbol
V
sec(clH)
V
sec(clL)
V
sec(on)
I
sec(on)
Parameter
Sec Clamp High
Sec Clamp Low
Sec Turn-on Voltage
Sec On Current
Test Conditions
I
sec
=20mA; V
OSC
=0V
I
sec
= -10mA
I
C
=10mA; V
OSC
=0V
V
sec
=10V; V
OSC
=0V;
I
C
=300mA
Min
Typ
22
25
4.5
4
Max
Unit
V
V
V
mA
3.5
5.5
3/14
VK05CFL
APPLICATION DESCRIPTION
Technology Overview
The VK05CFL is made by using STMicroelectronics proprietary VIPower M3-3 technology. This
technology allows the integration in the same chip both of the control part and the power stage. The power
stage is the “Emitter Switching”. It is made by putting in cascode configuration a bipolar high voltage
darlington with a low voltage MOSFET. This configuration provides a good trade-off between the bipolars
low ON drop with high breakdown voltage in OFF state, and the MOSFETS high switching speed. The
maximum theoretical working frequency is in the range of 300KHz.
Circuit description
The electrical scheme of the VK05CFL used as a self-oscillating converter to drive fluorescent tubes is
shown in Fig. 1.
Figure 1:
Application schematic
PTC
R2
diac
sec
Collector
C7
R1
C4
C13
C3
R4
L1s
C5
C10
osc
VK05CFL
Source
Bridge
+
Input Filter
C8
L2s
Lp
Tube
diac
sec
Collector
R5
osc
VK05CFL
C2
Source
C11
C6
This topology does not require the saturable transformer to set the working frequency. Two secondary
windings are wound on the main ballast choke Lp. These windings have two functions:1) to trigger the ON
state and 2) to provide the power supply to the device. A good trade-off for the ratio between the primary
winding Lp and the two secondary windings is 10:1; in order to minimize the power dissipated on the
resistors R4 - R5 and to guarantee sufficient voltage to supply the device.
The steady-state working frequency is set by the two capacitor C5 and C6. They are charged by a current
I
cap
≈
300µA. When the voltage on the capacitor reaches an internal fixed value the power stage is turned
OFF. By choosing the same value for C5 and C6 the circuit will work with a duty-cycle of 50%. During the
start-up, as the resonance frequency is higher than the steady-state frequency, the secondary voltage
falls lower than the device sustain voltage before the capacitor C5-6 is charged, switching OFF the device.
For this reason the circuit can work at different frequencies during the start-up and steady-state phases.
The resistor R2 and the capacitor C8 are needed to bias the internal diac in the low side device in order
to start-up the system. In the high side device the diac pin must be connected to the midpoint. R1 is the
pull-up resistor and C7 is the snubber capacitor.
Input filtering is realized by R4-C10 and R5-C11. It is necessary to have a proper supply voltage on the
input pin.
4/14
1
VK05CFL
Functional description
When the circuit is supplied, the capacitor C8 is charged by the resistor R2 till the voltage across it
reaches the internal diac threshold value (~ 30V). The low side switch is turned ON and consequently
current will flow from the HV rail to ground through the path formed by C3//C2, C4 and Lp (in case that the
pre-heating network is not present: PTC and C13 are not connected). The voltage drop on Lp is
“transferred” to the two secondary windings (wound in opposition) in order to confirm the ON state for the
low side device and the OFF state for the high side device. As soon as the low side device switches ON,
the capacitor C8 is discharged to ground by an internal HV diode to avoid diac restart.
In this preliminary phase the tube is OFF and the circuit will oscillate at the Lp-C4 series with (C3//C2)
resonance frequency
f
st – up
=
1
----------------------------
-
2π L c
⋅
C4
we can neglect C3//C2
As this frequency is higher than the steady-state one, the two devices will switch ON-OFF at this
frequency, as the voltage on the two secondary windings falls below the voltage needed to keep the
device on.
As soon as the tube is ignited the resonance frequency is reduced
≈
(Lp-C3//C2) and the circuit will work
at the steady-state frequency fixed by the two capacitors C5 and C6.
It is possible to calculate the steady-state frequency by these formulae:
5
-
T
on
= R
⋅
C
⋅
ln --
2
1
-- T = T
on
+ t
storage
+ t
(
dv
) ⁄ (
dt
)
-
2
1
-
f = --
T
(R = internal impedance)
Considering the VK05CFL board: R=12KΩ; C5=C6=1.2nF; t
storage
≈400nsec
; C7=680pF
⇒t
(dv)/(dt)
≈800nsec
;
the working frequency will be: f
≈35KHz.
In figure 2 and figure 3, the start-up phase without preheating is reported, while in figure 4 the main
waveforms in steady-state are shown.
Figure 2:
Start-up phase
I
device
midpoint
5/14
