Advance Information
VN16218
2.5 Gigabit SERDES Transceiver
Applications
•=
Fast serial backplane transceiver
•=
High-speed point-to-point links
General Description
The VN16218 is a low power single chip, 2.5GBd transceiver. It provides a 2.5GBd serial link interface in
the physical layer and includes a Serialize/Deserialize (SERDES) capability. Other functions include clock
generation, clock data recovery, and word synchronization. In addition, an internal loopback function is
provided for system debugging.
The VN16218 is ideal for 2.5 Gigabit, serial backplane and proprietary point-to-point applications. The
device supports both fiber-optic and copper media.
The transmitter section of the VN16218 accepts 20-bit wide TTL data and latches it on the rising edge of the
incoming Transmit Byte Clock (TBC) and serializes the data onto the TX± differential outputs, at a baud rate
that is twenty times the TBC frequency. The data is converted to a high-speed serial data stream. The
transmit PLL locks to the 125 MHz TBC. This clock is then multiplied by 20 to supply a 2.5 GHz serial clock
for parallel-to-serial conversion. The high-speed serial outputs can interface directly with copper cables or
PCB traces. Where optical transmission is required, the outputs can connect to a separate optical module.
When copper lines are the medium, equalization is available for improved performance.
The receiver section of the VN16218 accepts a serial data stream of 2.5 GBd and recovers 20 bit parallel
data. The receiver PLL locks on to the incoming serial signal and recovers the high-speed incoming clock
and data. The serial data is converted back into 20-bit parallel data format. Byte alignment is accomplished
by optional recognition of the K28.5+ comma character.
The recovered parallel data is sent to CMOS outputs, together with two 125 MHz clocks, RBC and RBCN,
that are 180 degrees out of phase from each other.
Features
•=
•=
•=
•=
•=
20-bit wide parallel Tx, Rx busses
20-bit LVTTL interface for transmit and
receive data at 125 MHz
125 MHz complementary receive and
byte clocks
Low Power Consumption
ESD rating >2000V (Human Body Model)
or >200V (Machine Model)
•=
•=
•=
•=
•=
Parallel loopback mode
Available in 14 mm x 14 mm
LQFP package
Differential PECL serial output
I/O power supply 3.3V
Core power supply 1.8 V
2001-11-09
Vaishali Semiconductor
Page 1
www.vaishali.com
747 Camden Avenue, Suite C Campbell
MDSN-0003-00
CA 95008
Ph. 408.377.6060
Fax 408.377.6063
VN16218
Figure 1. Functional Block Diagram
T[0:19]
Input Latch
D+
Parallel
to
D-
Serial
Converter
Line
Driver
Advance Information
TX+
TX-
TBC/REF
(125 MHz)
PLL Clock
Multiply X 20
R[0:19]
Serial
to
Parallel
Converter
Clock
Recovery
RX+
Mux 4:2
Equalizer
RX-
RCLK (125MHz)
Comma Detect
Loopback Enable
Figure 2. Pin Configuration
TEST2
NC
VDDP
VSSP
VDDP
TX-
TX+
VDDT
VSSA
VDDA
VSSA
VDDA
RX+
RX-
VDDA
RX0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RX10
RX1
RX11
VSSA
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VDDT
TX0
TX10
TX1
TX11
TX2
VSS
TX12
TX3
TX13
TX4
TX14
VDD
TX5
TX15
TX6
TX16
TX7
TX17
TX8
VSS
RX2
RX12
RX3
RX13
RX4
RX14
VDD
RX5
RX15
RX6
RX16
RX7
RX17
VDD
RX8
RX18
RX9
RX19
VSS
VDDA
NC
VSST
TBC/REF
NC
VSS
VDD
TEST1
EQEN
EN-CD
RX-F
EWR
2001-11-09
Vaishali Semiconductor
Page 2
www.vaishali.com
747 Camden Avenue, Suite C Campbell CA 95008
COM DET
RBC
RBCN
VSST
TX9
TX18
TX19
VSSA
MDSN-0003-00
Ph. 408.377.6060
Fax 408.377.6063
VN16218
Table 1. Pin Description
Name
VDDT
VSS
VDD
VDDA
TX[0:19]
Advance Information
Pin #
1, 73
7, 30, 41,
60
13, 31, 46,
53
21, 66, 69,
71
2, 4, 6
9,11, 14
16, 18, 20
23, 3, 5
8,10,12
15, 17, 19
22, 24
Type
P
P
P
P
I-TTL
3.3V power supply
Digital Ground. 0V
Description
Digital Power Supply. Connect to 1.8V
Analog Power Supply. Connect to 1.8V
Transmit Data Bus (bits 0 through 19). 20 bit transmit character.
Parallel data on this bus is clocked in on the rising edge of TBC.
The data bit corresponding to T0 is transmitted first
VSSA
NC
VSST
TBC/REF
25, 61, 70,
72
26, 29, 79
27, 40
28
P
Analog Ground. 0V
No Connection
P
I-TTL
TTL ground
Transmit Byte Clock / Reference Clock . A 125 MHz clock supplied
by the host system. The transmitter section accepts this signal as
the frequency reference clock. It is multiplied by 20 to generate the
serial bit clock and other internal clocks. The transmit side also
uses this clock as the transmit byte clock for the incoming parallel
data TX0 …. TX19. It also serves as the reference clock for the
receive portion of the transceiver
Test pin. For Vaishali use only. User should connect to V
DD
Equalizer enable
Enables comma detect
Receiver filter pin. For Vaishali use only.
Enable Internal WRAP mode. This pin is LOW in normal operation.
When enabled High, an internal loop-back path from the transmitter
to the receiver is enabled, TX+ is HIGH and TX- is LOW
Comma Detect. This output goes HIGH to signify that R0:6 contains
a comma character (0011111). COM_DET can be sampled on the
rising edge of TBC
Recovered Byte Clock. Recovered clock and its complement
derived from the RX± data rate divided by 20. The rising edge of
RBC corresponds to a new word on RX[0:19]
TEST1
EQEN
EN_CD
RX-F
EWR
32
33
34
35
36
I-TTL
I-TTL
I-TTL
O
I-TTL
COM_DET
37
O-TTL
RBC, RBCN
38, 39
O-TTL
2001-11-09
Vaishali Semiconductor
Page 3
www.vaishali.com
747 Camden Avenue, Suite C Campbell CA 95008
MDSN-0003-00
Ph. 408.377.6060
Fax 408.377.6063
VN16218
Advance Information
Name
RX[0:19]
Pin #
65, 63, 59
57, 55, 52
50, 48, 45
43, 64 ,62
58, 56, 54
51,49,47
44, 42
Type
O-TTL
Description
Receive Data Bus, Bits 0 through 19. 20 bit received data
character. Parallel data on this bus can be sampled on the rising
edge of RBC. R0 is the first bit received on RX+/RX-
RX+, RX-
TX+, TX-
68, 67
74, 75
I-diff
O diff
Receiver serial inputs. The device recognizes receiver inputs when
EWR is LOW
Transmitter serial ouputs. When EWR is LOW, the serialized
transmit data is available on these pins. When EWR is HIGH, TX+
is HIGH and TX- is LOW
High-speed output driver power supply. Connect to 1.8V
High speed output driver ground. 0V
Test pin for Vaishali internal use only. User should tie this pin to
GND for normal operation
VDDP
VSSP
TEST2
76,78
77
80
P
P
I-TTL
Legend: I = Input
O = Output
P = Power supply connection
Functional Block Description
PLL Clock Multiplier
The VN16218 employs a user-supplied 125 MHz clock both as a reference clock and as a Transmit Byte
Clock (TBC). The PLL Clock Multiplier multiplies the TBC by 20 to generate a baud rate clock of 2.5 GHz.
The TBC also clocks in the incoming parallel data.
Serializer (Parallel-to-Serial Converter)
Input data arrives at the T[0:19] bus as two parallel 10 bit characters and is latched into the input latch on
the rising edge of TBC. The data is serialized and transmitted on the TX differential outputs at a baud rate
of twenty times the frequency of TBC. Bit T0 is transmitted first. Incoming data is already encoded for
transmission using either the 8B/10B block code, as specified in the Fibre Channel specification, or an
equivalent edge-rich, DC-balanced code. If EWR is HIGH, the transmitter will be disabled, with TX+ HIGH
and TX- LOW. If EWR is LOW, the transmitter outputs serialized data. According to the fibre channel
specification, a transmission character is an encoded byte of 10 bits. The 20 bit interface of the VN16218
corresponds to two transmission characters, as shown in Table 2 below.
Table 2. Transmission Sequence and Mapping to Fibre Channel Character
Parallel Data Bits
8B/10Bit Position
Valid Comma Pos.
19
j
18
h
17
g
16
f
15
i
14
e
13
d
12
c
11
b
10
a
09
j
08
h
07
g
06
f
1
05
i
1
04
e
1
03
d
1
02
c
1
01
b
0
00
a
0
Last Data Bit Transmitted
First Data Bit Transmitted
2001-11-09
Vaishali Semiconductor
Page 4
www.vaishali.com
747 Camden Avenue, Suite C Campbell CA 95008
MDSN-0003-00
Ph. 408.377.6060
Fax 408.377.6063
VN16218
Advance Information
Equalizer
When EQEN is HIGH, the equalizer at the receiver is enabled, in order to correct for the frequency response
of the cable or other system components. The equalizer compensates for distortion introduced by the cable,
in order to maintain a low bit-error rate.
Input Latch
The transmitter accepts 20 bits wide single-ended parallel input T[0:19]. The TBC provided by the sender of
the transmit data is used as the transmit byte clock. The T[0:19] and TBC signals must be aligned as
shown in Figure 5. The T[0:19] data is latched on the rising edge of TBC.
Clock Recovery
When EWR is LOW, the VN16218 accepts differential high-speed inputs on the RX+ and RX- pins, extracts
the clock and retimes the data. The serial bit stream should be encoded in a Fibre Channel compatible
8B/10B, or equivalent format, in order to accomplish DC-balance and limited run length. Clock recovery
circuitry is self-contained and does not require external components. The baud rate of the data stream to be
recovered should be within 200 ppm of twenty times the TBC frequency. This allows oscillators at either
end of the link to be 125 MHz
±
100ppm.
Deserializer (Serial-to-Parallel Converter)
The re-timed serial bit stream is converted into two 10-bit parallel output characters. The VN16218 provides
a TTL recovered clock (RBC) at one-twentieth the serial baud rate. This is accomplished by dividing down
the high-speed clock that is phase locked to the serial data. The serial data is re-timed by the internal high-
speed clock and deserialized. Parallel data results, and is captured by the adjoining protocol logic on the
rising edge of RBC
Word Alignment
The VN16218 has 7-bit Fibre Channel comma character recognition, and data word alignment. Word
synchronization (with EN_CD HIGH), causes the VN16218 to constantly search the serial data for the
presence of the Fibre Channel ‘comma’ character. This pattern is ‘0011111XX’: the leading zero
corresponds to the first bit received. The comma sequence occurs only within special characters (K28.1,
K28.5 and K28.7) that are defined specifically for synchronization in Fibre Channel systems.
Improper alignment condition of the comma character is defined as;
1. The comma is not aligned within the 10 bit transmission character such that T0…T6 = ‘0011111’
2. The comma straddles the boundary between two 10-bit transmission characters.
When EN_CD is HIGH and an improperly aligned comma is encountered, the internal data is shifted so that
the comma character is aligned properly in R0:6, as shown in Table 2. The result is proper character and
word alignment. When an improperly aligned comma pattern causes changes in parallel data alignment,
some data that would have been presented at the parallel output port may be lost. However, the
synchronization character and subsequent data will be sent correctly and properly aligned. With EN_CD
LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern.
A ‘comma’ character drives COM_DET HIGH to notify the user that realignment of the parallel data field
may have occurred. The COM_DET pulse occurs simultaneously with the ‘comma’ character and has a
duration equal to that of the data. The COM_DET pulse is timed so that it is captured by the adjoining
protocol logic, on the rising edge of RBC. Figures 3 and 4 show functional waveforms for synchronization.
Figure 3 illustrates the situation when a ‘comma’ character is detected, but no phase adjustment is
necessary. The position of the COM_DET pulse is shown in relation to the ‘comma’ character on R0:6.
Figure 4 illustrates the situation when K28.5 is detected, but is out- of-phase, and a change in the output
data alignment is required. It should be noted that up to three characters before the ‘comma’ character may
be corrupted by the realignment process.
2001-11-09
Vaishali Semiconductor
Page 5
www.vaishali.com
747 Camden Avenue, Suite C Campbell CA 95008
MDSN-0003-00
Ph. 408.377.6060
Fax 408.377.6063
