®
VNB35NV04 / VNP35NV04
/
VNV35NV04 / VNW35NV04
“OMNIFET II”:
FULLY AUTOPROTECTED POWER MOSFET
TYPE
VNB35NV04
VNP35NV04
VNV35NV04
VNW35NV04
(*) For PowerSO-10 only
R
DS(on)
I
lim
V
clamp
10
10 mΩ (*)
30 A
40 V
1
3
1
D
2
PAK
PowerSO-10
™
n
LINEAR CURRENT LIMITATION
n
THERMAL SHUT DOWN
n
SHORT CIRCUIT PROTECTION
n
INTEGRATED CLAMP
n
LOW CURRENT DRAWN FROM INPUT PIN
n
DIAGNOSTIC FEEDBACK THROUGH INPUT
3
1
2
1
3
2
TO-220
TO-247
PIN
n
ESD PROTECTION
n
DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
n
COMPATIBLE WITH STANDARD POWER
MOSFET
ORDER CODES:
VNB35NV04
D
2
PAK
TO-220
VNP35NV04
VNV35NV04
PowerSO-10
™
TO-247
VNW35NV04
DESCRIPTION
The VNB35NV04, VNP35NV04, VNV35NV04,
VNW35NV04 are monolithic devices designed in
STMicroelectronics VIPower M0-3 Technology,
BLOCK DIAGRAM
intended for replacement of standard Power
MOSFETS from DC up to 25KHz applications.
Built in thermal shutdown, linear current limitation
and overvoltage clamp protect the chip in harsh
environments. Fault feedback can be detected by
monitoring the voltage at the input pin.
DRAIN
2
Overvoltage
Clamp
INPUT
1
Gate
Control
Over
Temperature
Linear
Current
Limiter
3
SOURCE
FC01000
July 2003
1/19
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
ABSOLUTE MAXIMUM RATING
Symbol
V
DS
V
IN
I
IN
R
IN MIN
I
D
I
R
V
ESD1
V
ESD2
P
tot
T
j
T
c
T
stg
Parameter
Drain-source Voltage (V
IN
=0V)
Input Voltage
Input Current
Minimum Input Series Impedance
Drain Current
Reverse DC Output Current
Electrostatic Discharge (R=1.5KΩ, C=100pF)
Electrostatic Discharge on output pin only
(R=330Ω, C=150pF)
Total Dissipation at T
c
=25°C
Operating Junction Temperature
Case Operating Temperature
Storage Temperature
Value
PowerSO-10
™
TO-220
Internally Clamped
Internally Clamped
+/-20
4.7
Internally Limited
-30
4000
16500
125
125
125
Internally limited
Internally limited
-55 to 150
208
D
2
PAK
TO-247
V
V
mA
Ω
A
A
V
V
W
°C
°C
°C
Unit
CONNECTION DIAGRAM (TOP VIEW)
INPUT
INPUT
INPUT
INPUT
INPUT
6
7
8
9
10
11
DRAIN
5
4
3
2
1
SOURCE
SOURCE
N.C.
SOURCE
SOURCE
(*) For the pins configuration related to TO-220, TO-247, D
2
PAK, see outlines at page 1.
CURRENT AND VOLTAGE CONVENTIONS
I
D
V
DS
DRAIN
I
IN
R
IN
INPUT
SOURCE
V
IN
2/19
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
THERMAL DATA
Symbol
R
thj-case
R
thj-amb
(*)
When
PowerSO-10
™
Thermal Resistance Junction-case}}} MAX
1
Thermal Resistance Junction-ambient MAX
50(*)
Parameter
Value
D2PAK
1
50(*)
TO-220
1
50
TO-247
0.6
30
Unit
°C/W
°C/W
mounted on a standard single-sided FR4 board with 50mm
2
of Cu (at least 35
µm
thick) connected to all DRAIN pins.
ELECTRICAL CHARACTERISTICS
(-40°C < T
j
< 150°C, unless otherwise specified)
OFF
Symbol
V
CLAMP
V
CLTH
V
INTH
I
ISS
V
INCL
I
DSS
Parameter
Drain-source Clamp
Voltage
Drain-source Clamp
Threshold Voltage
Input Threshold Voltage
Supply Current from Input
Pin
Input-Source Clamp
Voltage
Zero Input Voltage Drain
Current (V
IN
=0V)
Test Conditions
V
IN
=0V; I
D
=15A
V
IN
=0V; I
D
=2mA
V
DS
=V
IN
; I
D
=1mA
V
DS
=0V; V
IN
=5V
I
IN
=1mA
I
IN
=-1mA
V
DS
=13V; V
IN
=0V; T
j
=25°C
V
DS
=25V; V
IN
=0V
6
-1.0
Min
40
36
0.5
100
6.8
2.5
150
8
-0.3
30
75
Typ
45
Max
55
Unit
V
V
V
µA
V
µA
ON
Max
Symbol
Parameter
Static Drain-source On
Resistance
Test Conditions
V
IN
=5V; I
D
=15A; T
j
=25°C
V
IN
=5V; I
D
=15A; T
j
=150°C
PowerSO-10
10
20
D
2
PAK
TO-220 / TO-247
13
24
Unit
R
DS(on)
mΩ
3/19
1
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
ELECTRICAL CHARACTERISTICS (continued)
(T
j
=25°C, unless otherwise specified)
DYNAMIC
Symbol
g
fs
(*)
C
OSS
Parameter
Forward
Transconductance
Output Capacitance
Test Conditions
V
DD
=13V; I
D
=15A
V
DS
=13V; f=1MHz; V
IN
=0V
Min
Typ
35
1300
Max
Unit
S
pF
SWITCHING
Symbol
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
(di/dt)
on
Q
i
Parameter
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Turn-on Current Slope
Total Input Charge
Test Conditions
V
DD
=15V; I
D
=15A
V
gen
=5V; R
gen
=R
IN MIN
=4.7Ω
(see figure 1)
V
DD
=15V; I
D
=15A
V
gen
=5V; R
gen
=2.2KΩ
(see figure 1)
V
DD
=15V; I
D
=15A
V
gen
=5V; R
gen
=R
IN MIN
=4.7Ω
V
DD
=12V; I
D
=15A; V
IN
=5V
I
gen
=2.13mA (see figure 5)
Min
Typ
150
840
980
600
4
27
34
31
18
118
Max
500
2500
3000
1500
12
100
120
110
Unit
ns
ns
ns
ns
µs
µs
µs
µs
A/µs
nC
SOURCE DRAIN DIODE
Symbol
V
SD
(*)
t
rr
Q
rr
I
RRM
Parameter
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Test Conditions
I
SD
=15A; V
IN
=0V
I
SD
=15A; dI/dt=100A/µs
V
DD
=30V; L=200µH
Min
Typ
0.8
400
1.4
7
Max
Unit
V
ns
µC
A
Reverse Recovery Current (see test circuit, figure 2)
PROTECTIONS (-40°C < T
j
< 150°C, unless otherwise specified)
Symbol
I
lim
t
dlim
T
jsh
T
jrs
I
gf
E
as
Parameter
Drain Current Limit
Step Response Current
Limit
Overtemperature
Shutdown
Overtemperature Reset
Fault Sink Current
Single Pulse
Avalanche Energy
Test Conditions
V
IN
=6V; V
DS
=13V
V
IN
=6V; V
DS
=13V
Min
30
Typ
45
50
150
135
10
1.7
175
200
Max
60
Unit
A
µs
°C
°C
mA
J
V
IN
=5V; V
DS
=13V; T
j
=T
jsh
starting T
j
=25°C; V
DD
=24V
V
IN
=5V; R
gen
=R
IN MIN
=4.7Ω; L=24mH
(see figures 3 & 4)
15
20
(*) Pulsed: Pulse duration = 300µs, duty cycle 1.5%
4/19
2
VNB35NV04 / VNP35NV04 / VNV35NV04 / VNW35NV04
PROTECTION FEATURES
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power
MOSFET and can be used as a switch from DC up
to 25KHz. The only difference from the user’s
standpoint is that a small DC current I
ISS
(typ.
100
µ
A) flows into the INPUT pin in order to supply
the internal circuitry.
The device integrates:
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 45V, along with the rugged
avalanche characteristics of the Power MOSFET
stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT:
limits the drain current I
D
to I
lim
whatever the
INPUT pin voltages is. When the current limiter is
active, the device operates in the linear region, so
power dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction
temperature
may
reach
the
overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION:
these are based on sensing the chip temperature
and are not dependent on the input voltage. The
location of the sensing element on the chip in the
power stage area ensures fast, accurate detection
of the junction temperature. Overtemperature
cutout occurs in the range 150 to 190 °C, a typical
value being 170 °C. The device is automatically
restarted when the chip temperature falls of about
15°C below shut-down temperature.
- STATUS FEEDBACK:
in the case of an overtemperature fault condition
(T
j
> T
jsh
), the device tries to sink a diagnostic
current I
gf
through the INPUT pin in order to
indicate fault condition. If driven from a low
impedance source, this current may be used in
order to warn the control circuit of a device
shutdown. If the drive impedance is high enough
so that the INPUT pin driver is not able to supply
the current I
gf
, the INPUT pin will fall to 0V.
This
will not however affect the device operation:
no requirement is put on the current capability
of the INPUT pin driver except to be able to
supply the normal operation drive current I
ISS
.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit.
5/19
