VRS51L2070
Preliminary Datasheet
Rev 1.2
High-Performance Versa 8051 MCU
Overview
The VRS51L2070 is a high performance, 8051-based microcontroller
coupled with a fully integrated array of peripherals for addressing a
broad range of embedded design applications.
Based on a powerful 40-MIPS, single-cycle, 8051 microprocessor,
the VRS51L2070’s memory sub-system features 64KB of Flash
and 4352 bytes of SRAM.
Support peripherals include a hardware based arithmetic unit
capable of performing complex mathematical operations, JTAG
interface used for Flash programming and non-intrusive in-circuit
debugging/emulation, a precision internal oscillator (2% accuracy)
and a watchdog timer.
Communication and control of external devices is facilitated via an
assortment of digital peripherals such as an enhanced, fully
configurable SPI bus, an I²C interface, dual UARTs with dedicated
baud rate generators, 8 PWM controllers, 3 16-bit timers and 2 pulse
width counter modules.
The VRS51L2070 is powered by a 3.3 volt supply, can function
over the industrial temperature range, and is available in a
QFP-64 package (See VRS51L2170 datasheet for PLCC/QFP-44
packages - pin compatible with the industry standard 8051
microcontroller footprint/pin-out).
F
IGURE
1: VRS51L2070 F
UNCTIONAL
D
IAGRAM
Feature Set
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
8051 High Performance Single Cycle Processor
(Operation up to 40 MIPS)
64KB Flash Program Memory
(In-System/ln-Application Programmable)
4352 Bytes of SRAM (4KB + 256)
(Ext. 4K Bytes can be used for program or data memory)
JTAG Interface for Flash Programming and Non-Intrusive
Debugging/In-Circuit Emulation
MULT/DIV/ACCU Unit including Barrel Shifter
56 General Purpose I/Os (64-pin version)
2 Serial UARTs/2 Baud Rate Generators (16-bit)
Enhanced SPI Interface (fully configurable word size)
2
Fully Configurable I C Interface (Master/Slave)
16 External Interrupt Pins/Interrupt On Port Pin Change
16-bit General Purpose Timer/Counters
3 Timer Capture Inputs
2 Pulse Width Counter Modules
8 PWM Controller Outputs with Individual Timers
PWMs can be used as General Purpose Timers
Precision Internal Oscillator
Dynamic System Clock Frequency Adjustment
Power Saving Features
Power-On Reset/Brown-Out Detect
Watchdog Timer
Operating voltage: 3.1V to 3.6V
Operating Temperature -40°C to +85°C
VRS51L2070
Mult/Accu/Div
w/ 32-Bit Barrel
Shifter
Ports (7),
I/Os (56)
8051 Core
Single Cycle
40MHz
Flash
64K Bytes
JTAG
w/On-Chip
Emulation
o
F
IGURE
2: VRS51L2070 QFP-64 P
IN OUT
D
IAGRAMS
P1.2-CS2-PC1.1-RXD1-T2OUT*
P1.4-SS-T1OUT*
P1.3-CS3-TXD1
SDO-P1.5
SCK-SCL*-PC1.3-P1.6
SDI-SDA*-P1.7
RESET
RXD0-PC0.1-P3.0
T0OUT-P4.5
PWM0*-P5.0
PWM1*-P5.1
PWM2*-P5.2
PWM3*-P5.3
VSS
TXD0-P3.1
INT0-PC0.0-P3.2
INT1-PC1.0-P3.3
T0IN-SCL-EXBR0-PC0.3-P3.4
T1IN-SDA-EXBR1-P3.5
External Data
Bus Controller
SRAM
4352 Bytes
I
2
C
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
P1.1-CS1-T2EX
P1.0-CS0-T2IN
P4.4-T2OUT
VDD
P6.0-A0-T2EX*
P6.1-A1-T2IN*
P6.2-A2
P6.3-A3
P6.4-A4
P0.0-AD0
P0.1-AD1
P0.2-AD2
P0.3-AD3
SPI
On-Board
Oscillator
UARTs,
Baud Rate
Generators (2)
Crystal
Oscillator
Inputs
Dynamic
Clock
Control
10
11
12
13
14
15
VRS51L2070
QFP-64
42
41
40
39
38
37
36
35
34
Interrupt
Controller
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0.4-AD4
P0.5-AD5
P0.6-AD6
P0.7-AD7
P6.5-A5
P6.6-A6
P6.7-A7
PC1.2-T0EX-RXD1*
T1EX-TXD1*
P4.3-TDI
P4.2-TD0
CM0-ALE
P4.1-TMS
P2.7-A15-PWM7-TCK
P2.6-A14-PWM6-T0EX
P2.5-A13-PWM5-T1EX
Watch Dog
Timer
Pulse Width
Counters (2)
Power-On/
Reset
Timer Capture
Inputs (3)
Ramtron International Corporation
1850 Ramtron Drive Colorado Springs
Colorado, USA, 80921
♦
♦
♦
http://www.ramtron.com
MCU customer service: 1-800-943-4625, 1-514-871-2447 x 208
1-800-545-FRAM, 1-719-481-7000
WR-P3.6
RD-P3.7
VDD
PWM4*-P5.4
PWM5*-P5.5
PWM6*-P5.6
PWM7*-P5.7
XTAL1-P4.6
XTAL2-P4.7
VSS
T1OUT-P4.0
PWM0-A8-P2.0
PWM1-A9-P2.1
PWM2-A10-P2.2
TXD0*-PWM3-A11-P2.3
RXD0*-PWM4-A112-P2.4
PWMs/
Timers (8)
page 1 of 99
VRS51L2070
Pin Descriptions for QFP-64
T
ABLE
1: VRS51L2070 P
IN
D
ESCRIPTIONS FOR
QFP-64
PACKAGE
QFP -
64
1
P1.5
SDO
P1.6
2
SCK
SCL*
PC1.3
P1.7
3
SDI
SDA*
4
5
RESET
P3.0
RXD0
PC0.1
6
P4.5
T0OUT
P5.0
PWM0*
P5.1
PWM1*
P5.2
PWM2*
P5.3
PWM3*
VSS
P3.1
TXD0
P3.2
13
INT0
PC0.0
P3.3
14
INT1
PC1.0
P3.4
SCL
15
T0IN
PC0.3
EXBR0
P3.5
16
SDA
T1IN
EXBR1
P3.6
17
WR
P3.7
18
19
20
RD
VDD
P5.4
PWM4*
P5.5
PWM5*
P5.6
PWM6*
P5.7
PWM7*
O
O
O
O
I/O
I/O
I
I
I
I/O
I/O
I
I
I/O
O
I/O
O
VDD
I/O
I
Name
I/O
I/O
O
I/O
O
I/O
I
I/O
I
I/O
I/O
I/O
I
I
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
GND
I/O
O
I/O
I
Port 1.5
SPI Data output
Port 1.6
SPI Clock
I²C Clock (Alternate Pin)
Pulse Counter PC1 input 3
Port P1.7
SPI Data Input
I²C Data (Alternate Pin)
Reset
Port 3.0
UART0 RX pin
Pulse Counter PC0 input 1
Port 4.5
Timer 0 output
Port 5.0
PWM0 Output (Alternate Pin)
Port 5.1
PWM1 Output (Alternate Pin)
Port 5.2
PWM2 Output (Alternate Pin)
Port 5.3
PWM3 Output (Alternate Pin)
Device ground
Port 3.1
UART0 TX pin
Port 3.2
Interrupt 0 input
Pulse Counter PC0 input 0
Port 3.3
Interrupt 1 input
Pulse Counter PC1 input 0
Port 3.4
I²C clock
Timer 0 Input
Pulse Counter PC0 input 3
UART0 External Baud Rate Input
Port 3.5
I²C Data
Timer 1 Input
UART1 External Baud Rate input
Port 3.6
Ext Data memory access write signal
(active low)
Port 3.7
Ext Data memory access read signal (active
low)
Positive supply
Port 5.4
PWM4 Output (Alternate Pin)
Port 5.5
PWM5 Output (Alternate Pin)
Port 5.6
PWM6 Output (Alternate Pin)
Port 5.7
PWM7 Output (Alternate Pin)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Function
QFP -
64
24
P4.6
XTAL2
P4.7
VSS
P4.0
T1OUT
P2.0
PWM0
A8
P2.1
PWM1
A9
P2.2
PWM2
A10
P2.3
PWM3
TXD0*
A11
P2.4
PWM4
RXD0*
PC0.2
A12
P2.5
PWM5
T1EX
A13
P2.6
PWM6
T0EX
A14
P2.7
PWM7
TCK
A15
P4.1
TMS
CM0
ALE
P4.2
TDO
P4.3
TDI
TXD1*
T1EX
RXD1*
T0EX
PC1.2
P6.7
A7
P6.6
A6
P6.5
A5
Name
XTAL1
O
I/O
I
I/O
GND
I/O
O
I/O
O
O
I/O
O
O
I/O
O
O
I/O
O
O
O
I/O
O
I
I
O
I/O
O
I
O
I/O
O
I
O
I/O
O
I
O
I/O
I
I
O
I/O
O
I/O
I
O
I
I
I
I
I/O
O
I/O
O
I/O
O
I/O
Function
Crystal Oscillator (Output)
Port 4.6
Crystal Oscillator (Input)
Port 4.7
Device ground
Port 4.0
Timer 1 Output
Port 2.0
PWM0 Output
Ext. Address Bus A8
Port 2.1
PWM1 Output
Ext. Address Bus A9
Port 2.2
PWM2 Output
Ext. Address Bus A10
Port 2.3
PWM3 Output
UART0 TX pin (Alternate Pin )
Ext. Address Bus A11
Port 2.4
PWM4 Output
UART0 RX pin (Alternate Pin)
Pulse Counter PC0 input 2
Ext. Address Bus A12
Port 2.5
PWM5 output
Timer 1 EX input
Ext. Address Bus A13
Port 2.6
PWM6 output
Timer 0 EX input
Ext. Address Bus A114
Port 2.7
PWM7 output
JTAG TCK input
Ext. Address Bus A15
Port 4.1
JTAG TMS Input
JTAG Program mode
Ext Address Latch Enable
Port 4.2
JTAG TDO Line
Port 4.3
JTAG TDI line
UART1 TX pin (Alternate Pin)
Timer 1 EX input
UART1 RX pin (Alternate Pin)
Timer 0 EX input
Pulse Counter PC1 input 2
Port 6.7
Ext. Address 7 (Non-Multiplexed mode)
Port 6.6
Ext. Address 6 (Non-Multiplexed mode)
Port 6.5
Ext. Address 5 (Non-Multiplexed mode)
25
26
27
7
8
9
10
11
12
21
43
22
44
23
________________________________________________________________________________________________
www.ramtron.com
page 2 of 99
VRS51L2070
QFP -
64
45
P0.7
AD7
P0.6
AD6
P0.5
AD5
P0.4
AD4
P0.3
AD3
P0.2
AD2
P0.1
AD1
P0.0
AD0
P6.4
A4
P6.3
A3
P6.2
A2
P6.1
56
A1
T2IN*
P6.0
57
A0
T2EX*
58
59
VDD
P4.4
T2OUT
P1.0
60
CS0
T2IN
P1.1
61
CS1
T2EX
P1.2
CS2
62
RXD1
PC1.1
T2OUT
P1.3
63
CS3
TXD1
P1.4
64
SS
T1OUT*
I/O
O
I/O
O
I
I/O
O
I
I/O
O
I
I
O
I/O
O
O
I/O
I
O
Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
O
I/O
O
I
I/O
O
I
Port 0.7
P1.4-SS-T1OUT*
P1.3-CS3-TXD1
SDO-P1.5
SCK-SCL*-PC1.3-P1.6
SDI-SDA*-P1.7
RESET
RXD0-PC0.1-P3.0
T0OUT-P4.5
PWM0*-P5.0
PWM1*-P5.1
PWM2*-P5.2
PWM3*-P5.3
VSS
TXD0-P3.1
INT0-PC0.0-P3.2
INT1-PC1.0-P3.3
T0IN-SCL-EXBR0-PC0.3-P3.4
T1IN-SDA-EXBR1-P3.5
Function
P1.2-CS2-PC1.1-RXD1-T2OUT*
46
Port 0.6
Ext. Address/Data Bus AD6
Port 0.5
Ext. Address/Data Bus AD5
Port 0.4
Ext. Address/Data Bus AD4
Port 0.3
Ext. Address/Data Bus AD3
Port 0.2
Ext. Address/Data Bus AD2
Port 0.1
Ext. Address/Data Bus AD1
Port 0.0
Ext. Address/Data Bus AD0
Port 6.4
Ext. Address 4 (Non-Multiplexed mode)
Port 6.3
Ext. Address 3 (Non-Multiplexed mode)
Port 6.2
Ext. Address 2 (Non-Multiplexed mode)
Port 6.1
Ext. Address 1 (Non-Multiplexed mode)
Timer 2 input (Alternate)
Port 6.0
Ext. Address 0 (Non-Multiplexed mode)
Timer 2 EX Input (Alternate)
Positive supply
Port 4.4
Timer 2 Output
Port 1.0
SPI Chip Select 0
Timer 2 input
Port 1.1
SPI Chip Select 1
Timer 2 EX input
Port 1.2
SPI Chip Select 2
UART1 RX line
Pulse Counter PC1 input 1
Timer 2 Output Pin (Alternate Pin)
Port 1.3
SPI Chip Select 3
UART1 TX line
Port 1.4
SPI Slave Select input
Timer 1 Output (Alternate pin)
1
2
3
4
5
6
7
8
9
47
48
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
P1.1-CS1-T2EX
P1.0-CS0-T2IN
P4.4-T2OUT
VDD
P6.0-A0-T2EX*
P6.1-A1-T2IN*
P6.2-A2
P6.3-A3
P6.4-A4
P0.0-AD0
P0.1-AD1
P0.2-AD2
P0.3-AD3
Ext. Address/Data Bus AD7
49
50
51
10
11
12
13
14
15
VRS51L2070
QFP-64
42
41
40
39
38
37
36
35
34
52
53
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0.4-AD4
P0.5-AD5
P0.6-AD6
P0.7-AD7
P6.5-A5
P6.6-A6
P6.7-A7
PC1.2-T0EX-RXD1*
T1EX-TXD1*
P4.3-TDI
P4.2-TD0
CM0-ALE
P4.1-TMS
P2.7-A15-PWM7-TCK
P2.6-A14-PWM6-T0EX
P2.5-A13-PWM5-T1EX
54
55
________________________________________________________________________________________________
www.ramtron.com
page 3 of 99
WR-P3.6
RD-P3.7
VDD
PWM4*-P5.4
PWM5*-P5.5
PWM6*-P5.6
PWM7*-P5.7
XTAL1-P4.6
XTAL2-P4.7
VSS
T1OUT-P4.0
PWM0-A8-P2.0
PWM1-A9-P2.1
PWM2-A10-P2.2
TXD0*-PWM3-A11-P2.3
RXD0*-PWM4-A112-P2.4
VRS51L2070
F
IGURE
3: L
ARGER
V
IEW OF
VRS51L2070 QFP-64 P
ACKAGE PINOUT
P1.2-CS2-PC1.1-RXD1-T2OUT*
P1.4-SS-T1OUT*
P1.3-CS3-TXD1
SDO-P1.5
SCK-SCL*-PC1.3-P1.6
SDI-SDA*-P1.7
RESET
RXD0-PC0.1-P3.0
T0OUT-P4.5
PWM0*-P5.0
PWM1*-P5.1
PWM2*-P5.2
PWM3*-P5.3
VSS
TXD0-P3.1
INT0-PC0.0-P3.2
INT1-PC1.0-P3.3
T0IN-SCL-EXBR0-PC0.3-P3.4
T1IN-SDA-EXBR1-P3.5
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
P1.1-CS1-T2EX
P1.0-CS0-T2IN
P4.4-T2OUT
VDD
P6.0-A0-T2EX*
P6.1-A1-T2IN*
P6.2-A2
P6.3-A3
P6.4-A4
P0.0-AD0
P0.1-AD1
P0.2-AD2
P0.3-AD3
10
11
12
13
14
15
VRS51L2070
QFP-64
42
41
40
39
38
37
36
35
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0.4-AD4
P0.5-AD5
P0.6-AD6
P0.7-AD7
P6.5-A5
P6.6-A6
P6.7-A7
PC1.2-T0EX-RXD1*
T1EX-TXD1*
P4.3-TDI
P4.2-TD0
CM0-ALE
P4.1-TMS
P2.7-A15-PWM7-TCK
P2.6-A14-PWM6-T0EX
P2.5-A13-PWM5-T1EX
________________________________________________________________________________________________
www.ramtron.com
page 4 of 99
WR-P3.6
RD-P3.7
VDD
PWM4*-P5.4
PWM5*-P5.5
PWM6*-P5.6
PWM7*-P5.7
XTAL1-P4.6
XTAL2-P4.7
VSS
T1OUT-P4.0
PWM0-A8-P2.0
PWM1-A9-P2.1
PWM2-A10-P2.2
TXD0*-PWM3-A11-P2.3
RXD0*-PWM4-A112-P2.4
VRS51L2070
Instruction Set
The following table describes the instruction set of the
VRS51L2070. The instructions are binary code-compatible
and perform the same functions as industry standard
8051s.
T
ABLE
2: L
EGEND FOR
I
NSTRUCTION
S
ET
T
ABLE
Symbol
A
Rn
Direct
@Ri
rel
bit
#data
#data 16
addr 16
addr 11
Function
Accumulator
Register R0-R7
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two's complement offset byte
Direct bit address
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
Mnemonic
Description
Size
(bytes)
Instr.
Cycles
1
4
1
4
1
4
4
4
4
4
4
3
2
3
3
2
1
3
2
3
3
3
3
3
2
3
2
3
3+1
3+1
3*
2*
2*
1*
3
2
3
4
4
4
4+1
5+1
3+1
3+1
2+1
3+1
3+1
3+1
3+1
3 / 4 +1
3 / 4 +1
3/4+1
2+1
3+1
3+1
4 / 5 +1
3 / 4 +1
3 / 4 +1
4/5+1
3 / 4 +1
3 / 4 +1
1
1
3
4
Hex Code
T
ABLE
3: VRS51L2070 I
NSTRUCTION
S
ET
Mnemonic
Description
Size
(bytes)
Instr.
Cycles
2
3
3
2
2
3
3
2
2
3
3
2
2
2
3
3
2
2
3
3
2
2
2
4
2
3
3
2
3
3
2
3
3
2
3
3
2
3
3
2
3
3
1
1
1
1
1
1
1
Hex Code
Arithmetic instructions
Add register to A
ADD A, Rn
Add direct byte to A
ADD A, direct
Add data memory to A
ADD A, @Ri
Add immediate to A
ADD A, #data
Add register to A with carry
ADDC A, Rn
Add direct byte to A with carry
ADDC A, direct
Add data memory to A with carry
ADDC A, @Ri
Add immediate to A with carry
ADDC A, #data
Subtract register from A with borrow
SUBB A, Rn
Subtract direct byte from A with borrow
SUBB A, direct
Subtract data mem from A with borrow
SUBB A, @Ri
Subtract immediate from A with borrow
SUBB A, #data
Increment A
INC A
Increment register
INC Rn
Increment direct byte
INC direct
Increment data memory
INC @Ri
Decrement A
DEC A
Decrement register
DEC Rn
Decrement direct byte
DEC direct
Decrement data memory
DEC @Ri
Increment data pointer
INC DPTR
Multiply A by B
MUL AB
Divide A by B
DIV AB
Decimal adjust A
DA A
Logical Instructions
AND register to A
ANL A, Rn
AND direct byte to A
ANL A, direct
AND data memory to A
ANL A, @Ri
AND immediate to A
ANL A, #data
AND A to direct byte
ANL direct, A
AND immediate data to direct byte
ANL direct, #data
OR register to A
ORL A, Rn
OR direct byte to A
ORL A, direct
OR data memory to A
ORL A, @Ri
OR immediate to A
ORL A, #data
OR A to direct byte
ORL direct, A
OR immediate data to direct byte
ORL direct, #data
Exclusive-OR register to A
XRL A, Rn
Exclusive-OR direct byte to A
XRL A, direct
Exclusive-OR data memory to A
XRL A, @Ri
Exclusive-OR immediate to A
XRL A, #data
Exclusive-OR A to direct byte
XRL direct, A
Exclusive-OR immediate to direct byte
XRL direct, #data
Clear A
CLR A
Compliment A
CPL A
Swap nibbles of A
SWAP A
Rotate A left
RL A
Rotate A left through carry
RLC A
Rotate A right
RR A
Rotate A right through carry
RRC A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
28h-2Fh
25h
26h-27h
24h
38h-3Fh
35h
36h-37h
34h
98h-9Fh
95h
96h-97h
94h
04h
08h-0Fh
05h
06h-07h
14h
18h-1Fh
15h
16h-17h
A3h
A4h
84h
D4h
58h-5Fh
55h
56h-57h
54h
52h
53h
48h-4Fh
45
46h-47h
44h
42h
43h
68h-6Fh
65h
66h-67h
64h
62h
63h
E4h
F4h
C4h
23h
33h
03h
13h
Boolean Instruction
Clear Carry bit
CLR C
Clear bit
CLR bit
Set Carry bit to 1
SETB C
Set bit to 1
SETB bit
Complement Carry bit
CPL C
Complement bit
CPL bit
Logical AND between Carry and bit
ANL C,bit
Logical AND between Carry and not bit
ANL C,#bit
Logical ORL between Carry and bit
ORL C,bit
Logical ORL between Carry and not bit
ORL C,#bit
Copy bit value into Carry
MOV C,bit
Copy Carry value into Bit
MOV bit,C
Data Transfer Instructions
Move register to A
MOV A, Rn
Move direct byte to A
MOV A, direct
Move data memory to A
MOV A, @Ri
Move immediate to A
MOV A, #data
Move A to register
MOV Rn, A
Move direct byte to register
MOV Rn, direct
Move immediate to register
MOV Rn, #data
Move A to direct byte
MOV direct, A
Move register to direct byte
MOV direct, Rn
Move direct byte to direct byte
MOV direct, direct
Move data memory to direct byte
MOV direct, @Ri
Move immediate to direct byte
MOV direct, #data
Move A to data memory
MOV @Ri, A
Move direct byte to data memory
MOV @Ri, direct
Move immediate to data memory
MOV @Ri, #data
Move immediate to data pointer
MOV DPTR, #data
MOVC A, @A+DPTR
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
3
2
3
1
1
2
3
C3h
C2h
D3h
D2h
B3h
B2h
82h
B0h
72h
A0h
A2h
92h
E8h-EFh
E5h
E6h-E7h
74h
F8h-FFh
A8h-AFh
78h-7Fh
F5h
88h-8Fh
85h
86h-87h
75h
F6h-F7h
A6h-A7h
76h-77h
90h
93h
83h
E2h-E3h
E0h
F2h-F3h
F0h
C0h
D0h
C8h-CFh
C5h
C6h-C7h
D6h-D7h
11h-F1h
12h
22h
32h
01h-E1h
02h
80h
40h
50h
20h
30h
10h
73h
60h
70h
B5h
B4h
B8h-BFh
B6h-B7h
D8h-DFh
D5
00h
A5h
A5h
A5h
Move code byte relative DPTR to A
Move code byte relative PC to A
MOVC A, @A+PC
MOVX
Move external data (A8) to A
A,{MPAGE, @Ri}
Move external data (A16) to A
MOVX A, @DPTR
MOVX
Move A to external data (A8)
{MPAGE, @Ri},A
Move A to external data (A16)
MOVX @DPTR, A
Push direct byte onto stack
PUSH direct
Pop direct byte from stack
POP direct
Exchange A and register
XCH A, Rn
Exchange A and direct byte
XCH A, direct
Exchange A and data memory
XCH A, @Ri
Exchange A and data memory nibble
XCHD A, @Ri
Branching Instructions
Absolute call to subroutine
ACALL addr 11
Long call to subroutine
LCALL addr 16
Return from subroutine
RET
Return from interrupt
RETI
Absolute jump unconditional
AJMP addr 11
Long jump unconditional
LJMP addr 16
Short jump (relative address)
SJMP rel
Jump on carry = 1
JC rel
Jump on carry = 0
JNC rel
Jump on direct bit = 1
JB bit, rel
Jump on direct bit = 0
JNB bit, rel
Jump on direct bit = 1 and clear
JBC bit, rel
Jump indirect relative DPTR
JMP @A+DPTR
Jump on accumulator = 0
JZ rel
Jump on accumulator 1= 0
JNZ rel
Compare A, direct JNE relative
CJNE A
, direct, rel
Compare A, immediate JNE relative
CJNE A, #d, rel
Compare reg, immediate JNE relative
CJNE Rn, #d, rel
Compare ind, immediate JNE relative
CJNE @Ri, #d, rel
Decrement register, JNZ relative
DJNZ Rn, rel
Decrement direct byte, JNZ relative
DJNZ direct, rel
Miscellaneous Instruction
No operation
NOP
If PCON.4 is 0 (reset Value): NOP
NOP
MOV @RamPtr,A
MOV A,@RamPtr
If MSB (@RamPtr) == 0
Accumulator value is written
in SFR{1,@RamPtr[6:0]}
If MSB (@RamPtr) == 1
SFR{1,@RamPtr[6:0]}
is written in Accumulator
Rn:
Any of the register R0 to R7
@Ri:
Indirect addressing using Register R0 or R1
#data:
immediate Data provided with Instruction
#data16:
Immediate data included with instruction
bit:
address at the bit level
rel:
relative address to Program counter from +127 to –128
Addr11: 11-bit address range
Addr16: 16-bit address range
#d:
Immediate Data supplied with instruction
________________________________________________________________________________________________
www.ramtron.com
page 5 of 99
