The VS-702 is a SAW Based Voltage Controlled Oscillator that achieves low phase noise and very low jitter performance. The VS-
702 is housed in an industry standard hermetically sealed LCC package and available in tape and reel.
Features
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Industry Standard Package, 5.0 x 7.5 x 2.0 mm
ASIC Technology for Ultra Low Jitter
0.100 ps-rms typical across 12 kHz to 20 MHz BW
0.120 ps-rms typical across 50 kHz to 80 MHz BW
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•
•
•
•
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•
Output Frequencies from 150 MHz to 1 GHz
3.3 V Operation
LV-PECL or LVDS Configuration with Fast Transition Times
Improved Temperature Stability over Standard VCSO (±20 ppm)
Output Disable Feature
0/70°C or -40/85°C operating temperature
Product is free of lead and compliant to EC RoHS Directive
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SONET, SDH
Applications
Ideal for PLL circuits for clock smoothing and frequency
translation
Synchronous Ethernet
Fiber Channel
LAN / WAN
Test and Measurement
Block Diagram
Complementary
Output
Output
V
DD
BAW
SAW
V
C
E/D
Page1
Gnd
Performance Specifications
Table 1. Electrical Performance
Parameter
Voltage
1
Current (No Load)
Nominal Frequency
2
Absolute Pull Range
3,6
Linearity
3
Gain Transfer Positive
3
(See pg 5)
Temperature Stability
3
Mid Level
3
Single Ended Swing
3
Double Ended Swing
3
Current
Rise Time
4
Fall Time
4
Symmetry
3
Jitter (12 kHz - 20 MHz BW)622.08MHz
5
Jitter (50 kHz - 80 MHz BW)155.52MHz
5
Period Jitter, RMS (622.08MHz)
7
Period Jitter, Peak - Peak (622.08MHz)
7
Spurious Suppression
2
Control Voltage
Control Voltage Range for APR
Control Voltage Input Impedance
Control Voltage Modulation BW
Output Enabled, Option A
Output Disabled, Option A
Output Enabled, Option C
Output Disabled, Option C
Operating Temperature
Package Size
1]
2]
3]
4]
5]
6]
7]
Symbol
V
DD
I
DD
Min
Supply
2.97
Frequency
Typical
3.3
70
Maximum
3.63
90
1000
Units
V
mA
MHz
ppm
%
ppm/V
ppm
f
N
APR
Lin
K
V
f
STAB
150
±50
5
+100
±20
Outputs
V
DD
-1.5
V
DD
-1.3
750
1.5
10
V
DD
-1.2
V
mV-pp
V-pp
I
OUT
t
R
t
F
SYM
фJ
фJ
фJ
фJ
45
50
0.1
0.12
2.5
16
-60
V
C
Z
IN
BW
V
IH
V
IL
V
IL
V
IH
T
OP
0.3
75
50
Enable/Disable
0.7*V
DD
20
500
500
55
0.250
0.300
3.0
24
-50
3.0
mA
ps
ps
%
ps-rms
ps-rms
ps
ps
dBc
V
KΩ
kHz
V
V
0.3*V
DD
0.2*V
DD
0.7*V
DD
0/70 or -40/85
5.0 x 7.5 x 2.0
°C
mm
The VS-702 power supply should be filtered, eg, 0.1 and 0.01uF to ground
See Standard Frequencies and Ordering Information tables for more specific information
Parameters are tested with production test circuit below (Fig 1).
Measured from 20% to 80% of a full output swing (Fig 2).
Integrated across stated bandwidth.
Tested with Vc = 0.3V to 3.0V unless otherwise stated in part description
Broadband Period Jitter measured using Lecroy Wavemaster 8600A 6 GHz Oscilloscope, 25K samples taken. See application note.
Fig 1: Test Circuit
Vc (-1.0V to +1.7V)
1
6
Vcc (+2V)
Fig 2: LVPECL Waveform
t
R
t
F
SYM = 100 x t
A
/ t
R
OD (-1.3V), OE (Open)
2
5
COutput
Vee (-1.3V)
3
4
Output
50
Ω
50
Ω
Test Circuit Notes:
1) To Permit 50
Ω
Measurement of Outputs, all DC Inputs are Biased Down 1.3V.
2) All Voltage Sources Contain Bypass Capacitors to Minimize Supply Noise.
3) 50
Ω
Terminations are Within Test Equipment.
t
A
t
R
Page2
Outline Drawing & Pad Layout
XXX.XXXX
VS702 YWW
CCC-CCCC
XXX.XX
XXXMXXX
Dimensions in inches (mm)
Table 2. Pin Out
Pin
1
2
3
4
5
6
Symbol
V
C
OE
GND
Output
COutput
Function
VCXO Control Voltage
Enable/Disable
**See Ordering Options**
Case and Electrical Ground
Output
Complementary Output
Power Supply Voltage (3.3V ±10%)
V
DD
Typical Phase Noise
Typical Gain
VS-702 @ 622.08 MHz
200
120
150
110
100
100
50
Gain (ppm/V)
Pull (ppm)
0
0
-50
0.5
1
1.5
2
2.5
3
90
Series1
Series2
80
-100
70
-150
-200
Vc (volts)
60
Page3
Suggested Output Load Configurations
The VS-702 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 3. There are numerous application notes on
terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, and a pull-up/pull-down scheme as
shown in Figure 5. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Figure 3 Standard PECL Output Configuration
Figure 4 Single Resistor Termination Scheme
Resistor values are typically 120 to 240 ohms
Figure 5 Pull-Up Pull-Down Termination
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow
simulation. The VS-702 family is capable of meeting the following qualification tests:
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Solderability
Gross and Fine Leak
Resistance to Solvents
Moisture Sensitivity Level
Contact Pads
Mechanical Vibration
Conditions
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2015
MSL 1
Gold over Nickel
MIL-STD-883,
Typical Characteristics - Phase Noise
Method 2002
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not
implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet.
Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Permanent damage is
also possible if OD or Vc is applied before Vcc.
Table 4. Absolute Maximum Ratings
Parameter
Power Supply
Output Current
Voltage Control Range
Storage Temperature
Soldering Temp/Time
Symbol
V
DD
I
OUT
V
C
TS
T
LS
Ratings
0 to 6
25
0 to V
DD
-55 to 125
260 / 40
Unit
V
mA
V
°C
°C / sec
Although ESD protection circuitry has been designed into the VS-702 proper precautions should be taken when handling
and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing
