VSC7216-06
Data Sheet
Multi-Gigabit Interconnect Chip with Extended Temperature Range
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F
EATURES
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Fast-Locking CRU
Per-Channel Serial Tx-to-Rx and Parallel Rx-to-Tx
Internal Loopback Modes
0.98Gb/s to 1.36Gb/s or 0.49Gb/s to 0.68Gb/s
Automatic Lock-to-Reference
Three Levels of Deskew vs. Latency
JTAG Boundary Scan Support for TTL I/O
Built-In Self Test
2.5V Supply, 700mW Typ
256-Pin, 27mm BGA or 21mm Fine Pitch BGA
Package
Extended Temperature Operation: -40°C (ambient) to
100°C (case)
Four ANSI X3T11 Fibre Channel and IEEE 802.3z
Gigabit Ethernet-Compliant Transceivers
Over 8Gb/s Duplex Raw Data Rate
User-Selectable Half-Speed Mode
Redundant PECL Tx Outputs and Rx Inputs
8B/10B Encoder/Decoder per Channel; Optional
Encoder/Decoder Bypass Operation
ASIC-Friendly
™
Timing Options for Transmitter
Parallel Input Data
Elastic Buffers for Intra-/Inter-Chip Cable Deskewing
and Channel-to-Channel Alignment
Tx/Rx Rate Matching via IDLE Insertion/Deletion
Selectable PECL Input Termination
Received Data Aligned to Local REFCLK or to
Recovered Clock
PECL Rx Signal Detect and Cable Equalization
On-Chip Termination
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A
PPLICATIONS
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Backplane Interconnect for Data Communications
Serial Bus Extension
Gigabit Ethernet Transceiver
Fibre Channel Transceiver
Serial Link Redundancy
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G
ENERAL
D
ESCRIPTION
The VSC7216-06 is a quad 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high bandwidth
interconnection between busses, backplanes, or other subsystems. Four Fibre Channel and Gigabit Ethernet-compliant
transceivers provide up to 8.32Gb/s of duplex raw data transfer. Each channel can be operated at a maximum data
transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 392Mb/s (8 bits at 49MHz). For the entire chip in
duplex mode, the maximum aggregate transfer rate is 8.7Gb/s. The VSC7216-06 contains four 8B/10B encoders,
serializers/deserializers (SerDes), 8B/10B decoders, and elastic buffers, which provide a simple interface for
transferring data serially and recovering it on the receive side. The VSC7216-06 can also be configured to operate as
four non-encoded 10-bit transceivers.
G52416, Revision 4.0
December 2006
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896
Internet: www.vitesse.com
1 of 40
VSC7216-06
Data Sheet
Transmitter
Receiver
10
Clk/Data
Recovery
PSDETD
RSDETD
10
3
Clk/Data
Recovery
PSDETC
RSDETC
10
Clk/Data
Recovery
PSDETB
RSDETB
10
Clk/Data
Recovery
PSDETA
RSDETA
8
3
8B/10B
8B/10B
Decode
Decode
RXFIFO[1:0]
8
8
8B/10B
Decode
3
Elastic
Buffer
RXFIFO[1:0]
8
Elastic
Buffer
8
Elastic
Buffer
8
8B/10B
Decode
RXFIFO[1:0]
8B/10B
Decode
3
Elastic
Buffer
8
8
PTXEND
8
8B/10B
Encode
10
RTXEND
PTXENC
8
8B/10B
Encode
RTXENC
PTXENB
8
8B/10B
Encode
10
RTXENB
PTXENA
8
8B/10B
Encode
10
RTXENA
10
8
TD[7:0]
C/DD
WSEND
D Q
LBEND[1:0]
RXP/RD
LBTXD
RREF
PTXD+ PRXD+
PTXD- PRXD-
RTXD+ RRXD+
RTXD- RRXD-
RD[7:0]
IDLED
KCHD
ERRD
8
VSC7216-06 Block Diagram
RC7:0)
IDLEC
KCHC
ERRC
RCLKC
RCLKCN
TC[7:0]
C/DC
WSENC
D Q
LBENC[1:0]
RXP/RC
LBTXC
RREF
PTXC+ PRXC+
PTXC- PRXC-
RTXC+ RRXC+
RTXC- RRXC-
8
TB[7:0]
C/DB
WSENB
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LBENA[1:0]
RXP/RA
LBTXA
RREF
PTXA+ PRXA+
PTXA- PRXA-
RTXA+ RRXA+
RTXA- RRXA-
4
Tx Clock
REFCLK
TMODE(2:0)
RMODE[1:0]
TBERRA
TBERRB
TBERRC
TBERRD
RESETN
ENDEC
BIST
CREG
D Q
LBENB[1:0]
RXP/RB
LBTXB
RREF
PTXB+ PRXB+
PTXB- PRXB-
RTXB+ RRXB+
RTXB- RRXB-
RB[7:0]
IDLEB
KCHB
ERRB
RCLKB
RCLKBN
8
TA[7:0]
C/DA
WSENA
D Q
RA[7:0]
IDLEA
KCHA
ERRD
RXFIFO[1:0]
WSI
FLOCK
Channel
Align
RCLKA
RCLKAN
WSO
KCHAR
x20/x10
Clock Gen
JTAG
Boundary
Scan
TDO
TBCA
TBCB
TBCC
TBCD
DUAL
RATE
REFCLKP
REFCLKN
CAP0 CAP1
TRSTN
TMS
TDI
TCK
Downloaded by pm_virendrakumar@yahoo.com on February 14, 2007 from Vitesse.com
G52416, Revision 4.0
December 2006
VSC7216-06
Data Sheet
Notation
Downloaded by pm_virendrakumar@yahoo.com on February 14, 2007 from Vitesse.com
In this document, each of the four channels are identified as channel A, B, C or D. When discussing a signal on any
specific channel, the signal will have the channel letter embedded in the name, for example, TA[7:0]. When referring
to the common behavior of a signal that is used on each of the four channels, a lower case “n” is used in the signal
name, for example, Tn[7:0]. Differential signals (for example, PTXA+ and PTXA-), may be referred to as a single
signal (for example, PTXA), by dropping reference to the + and -. REFCLK refers to either the PECL/TTL input pair
REFCLKP/REFCLKN, which can be differential PECL (using both REFCLKP and REFCLKN), or single-ended
TTL (using REFCLKP and leaving REFCLKN open).
Clock Synthesizer
Depending on the state of the DUAL input, the VSC7216-06 clock synthesizer multiplies the reference frequency
provided on the REFCLK input by 10 (DUAL is LOW) or 20 (DUAL is HIGH) to achieve a baud rate clock between
0.98GHz and 1.36GHz. The on-chip Phase-Locked Loop (PLL) uses three external 0.1µF capacitors; one connected
between CAP0 and CAP1, and two capacitors to ground, to control the Loop Filter. See
Figure 1.
These capacitors
should be of multilayer ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature
coefficient (NPO is preferred but X7R may be acceptable). These capacitors are used to minimize the impact of
common-mode noise on the Clock Multiplier Unit (CMU), especially power supply noise. Higher value capacitors
provide better robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply noise
sensitivity will vary with temperature. Larger values are better but 0.1µF is adequate. These components should be
isolated from noisy traces.
CAP0
VSC7216-06
CAP1
C
2
C
1
C
3
C1 = C2 = C3 = >0.1µF
Multilayer Ceramic
Surface Mount
NPO (preferred) or X7R
5V Working Voltage Rating
Figure 1. Loop Filter Capacitors (best circuit)
The REFCLK signal can be either single-ended TTL or differential LVPECL. If TTL, connect the TTL input to
REFCLKP and terminate REFCLKN as shown in
Figure 23 on page 27.
If LVPECL, connect the inputs to
REFCLKP and REFCLKN. Internal biasing resistors sets the proper DC Level to V
DD
/2.
Serial and parallel data rates for all channels may be halved by means of the RATE pin. When RATE is HIGH, the
chip is in full-speed mode (default mode of operation), and when LOW, the half-speed mode is selected.
Table 1
shows the interaction of the DUAL and RATE inputs.
Table 1. Using the RATE Input to Achieve Half-Speed Operation
RATE Pin
0
0
1
1
DUAL Pin
0
1
0
1
Clock Multiplication
Factor
x10
x20
x10
x20
Serial Link Speed
500Mb/s
500Mb/s
1Gb/s
1Gb/s
Parallel Data Rate
50Mb/s
50Mb/s
100Mb/s
100Mb/s
REFCLK Frequency
50MHz
25MHz
100MHz
50MHz
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G52416, Revision 4.0
December 2006
VSC7216-06
Data Sheet
Internal Voltage Regulator
There is a voltage regulator on-chip that requires an external capacitance of at least 4.7μF attached from its output,
CREG, to GND. A capacitor value of 10μF is recommended.
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Analog Power Supply Considerations
The VSC7216-06 contains an internal PLL that is powered by separate analog power supply pins denoted as VDDA/
VSSA. The performance of the VSC7216-06 is particularly sensitive to noise on these pins, therefore, special care
should be taken to filter out any such noise. It is recommended that V
DD
pass through a ferrite bead and onto the
V
DDA
pin, which should be bypassed with a pair of capacitors of 0.1µF and 10µF.
T
RANSMITTER
F
UNCTIONAL
D
ESCRIPTION
Transmitter Data Bus
Each VSC7216-06 transmit channel has an 8-bit input transmit data character, Tn[7:0], and two control inputs, C/Dn
and WSENn. The C/Dn input determines whether a normal data character or a special K-character is transmitted, and
the WSENn input initiates transmission of a 16-character “Word Sync Sequence” used to align the receive channels.
These data and control inputs are clocked either on the rising edge of REFCLK, on the rising edge of TBCn, or within
the data eye formed by TBCn. When not using REFCLK, each channel uses either its own TBCn input, or uses the
TBCA input. The transmit interface mode is controlled by TMODE[2:0] as shown in
Table 2.
When used, the TBCn inputs must be frequency-locked to REFCLK. No phase relationship is assumed. A small skew
buffer is provided to tolerate phase drift between TBCn and REFCLK. This buffer is recentered by the RESETN
input, and the total phase drift after recentering must be limited to +/- 180° (where 360° is one character time). Each
channel has an error output, TBERRn, that is asserted HIGH to indicate that the phase drift between TBCn and
REFCLK has accumulated to the point that the elastic limit of the skew buffer has been exceeded and a transmit data
character has been either dropped or duplicated. This error can not occur when input timing is referenced to
REFCLK. The TBERRn output timing is identical to the low-speed receiver outputs, as selected by RMODE[1:0] in
Table 6 on page 11.
Table 2. Transmit Interface Input Timing Mode
TMODE[2:0]
000
001
010
011
100
101
110
111
Input Timing Reference
REFCLK Rising Edge
Reserved
TBCA Rising Edge
TBCn Rising Edge
TBCA Data Eye
TBCn Data Eye
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G52416, Revision 4.0
December 2006
VSC7216-06
Data Sheet
Figures
2, 3,
and
4
show possible relationships between data and control inputs and the selected input timing source.
Figure 2
shows how REFCLK is used as an input timing reference.
Figure 3
and
Figure 4
show how TBCn is used as
an input timing reference. When TBCn is used to define a data eye, as shown in
Figure 4,
it functions as an additional
data input that simply toggles every cycle.
The REFCLK and TBCn inputs are not used directly to clock the input data. Instead, an internal PLL generates edges
aligned with the appropriate clock. The arrows on the rising edges of these signals define the reference edge for the
internal phase detection logic. An internal clock is generated at 1/10
th
the serial transmit data rate that is locked to the
selected input timing source. This is especially important when DUAL is HIGH and input timing is referenced to
REFCLK, since the falling edge is NOT used. In this mode, the internal clock’s rising edges are placed coincident
with REFCLK’s rising edges, halfway between REFCLK’s succeeding rising edges.
A similar situation exists when TBCn is used to define a data eye, only the rising edges of TBCn are used to define
the external data timing. The internal clock active edges are placed at 90° and 270° points between consecutive TBCn
rising edges (which are assumed to be 360° apart).
Downloaded by pm_virendrakumar@yahoo.com on February 14, 2007 from Vitesse.com
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
Tn[7:0]
C/Dn
WSENn
Valid
Valid
Valid
Figure 2. Transmit Timing, TMODE[2:0] = 000
TBCA
or
TBCn
Tn[7:0]
C/Dn
WSENn
Valid
Valid
Valid
Figure 3. Transmit Timing, TMODE[2:0] = 10x
0°
TBCA
or
TBCn
Tn[7:]
C/Dn
WSENn
90°
180°
270°
360°
Valid
Valid
Valid
Figure 4. Transmit Timing, TMODE[2:0] = 11x (ASIC-Friendly TIming)
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G52416, Revision 4.0
December 2006
