The VSC8115 contains an on-chip phase locked-loop (PLL) consisting of a phase/frequency detector (PFD), a loop
filter using one external capacitor, an LC-based voltage-controlled oscillator (VCO), and a programmable frequency
divider. The PFD compares the phase relationship between the VCO output and an external 19.44 MHz LVTTL
reference clock to make coarse adjustments to the VCO block so that its output is held within ±500 ppm of the
reference clock. The PFD also compares the phase relationship between the VCO output and the serial data input to
make fine adjustments to the VCO block. The loop filter converts the phase detector output into a smooth DC voltage.
This DC voltage is used as the input to the VCO block whose output frequency is a function of the input voltage. The
VCO output signal is fed into a programmable frequency divider that generates either a 622.08 Mbps signal if STS12
is HIGH, or a 155.52 Mbps signal if STS12 is LOW, back to the PFD.
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Lock Detection
The VSC8115 features a lock detection for the PLL. The lock detect (LOCKDET) output goes HIGH to indicate that
the PLL is locked to the serial data inputs and that valid data and clock are present at the high-speed differential
outputs. If LOCKDET output is LOW, then either the PLL is forced to lock to the REFCLK input or the VCO has
drifted away from the local reference clock by more than 500 ppm.
LOCKDET requires that the reference clock be present to operate properly.
Signal Detection
The VSC8115 has a signal detect (SD) input and a lock-to-reference (LOCKREFN) input. The SD pin is a LVPECL
input and the LOCKREFN pin is a LVTTL input. These two control pins are used to indicate an LOS condition and
are connected inside the part as shown in
Figure 1
on page 3. If either one of these two inputs goes LOW and
BYPASS is LOW, the VSC8115 will enter a Loss of Signal (LOS) state, and will hold the DATAOUT± output at logic
LOW state. During the LOS state, the VSC8115 will also hold the output clock CLKOUT± to within ±500 ppm of the
REFCLK. See
Table 1
on page 3.
Most optical modules have an SD output. This SD output indicates that there is sufficient optical power and is
typically active HIGH. If the SD output on the optical module is LVPECL, it should be connected directly to the SD
input on the VSC8115, and the LOCKREFN input be tied HIGH. If the SD output is LVTTL, it should be connected
directly to the LOCKREFN input, and the SD input should be tied HIGH.
The SD and LOCKREFN inputs also can be used for other applications when it is required to hold the CLKOUT±
output to within ±500 ppm of the reference clock and to force the DATAOUT± output to the logic LOW state.
Reference Clock
Upon powering up the VSC8115, it is recommended that the reference clock be present at least 40 bit times before the
data signal is introduced.
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G52272 Revision 4.4
October 6, 2005
VSC8115
Datasheet
PLL Bypass Operation
The BYPASS pin is intended for use in production test and should be set at logic LOW in normal operation. If both
BYPASS and STS12 pins are set at logic HIGH, the VSC8115 will bypass the PLL and present an inverted version of
the REFCLK to the clock output CLKOUT±. The REFCLK’s rising edge is used to capture data at DATAIN± and
transmit data at DATAOUT±. This bypass operation can be used to facilitate the board debugging process.
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DATAIN±
2
2
DATAOUT±
PLL Clock
(on-chip)
REFCLK
STS12
BYPASS
0
1
2
CLKOUT±
LOCKREFN
SD
LOS
(on-chip)
Figure 1. Control Diagram for Signal Detection and PLL Bypass Operation
Table 1. Signal Detect and PLL Bypass Operation Control
STS12
1
1
1
1
1
0
0
0
0
0
BYPASS
0
0
0
0
1
0
0
0
0
1
LOCKREFN
1
1
0
0
X
1
1
0
0
X
SD
1
0
1
0
X
1
0
1
0
X
DATAOUT
DATAIN
LOW
LOW
LOW
DATAIN
DATAIN
LOW
LOW
LOW
Not allowed
CLKOUT
PLL clock
PLL clock
PLL clock
PLL clock
REFCLK
PLL clock
PLL clock
PLL clock
PLL clock
Not allowed
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G52272 Revision 4.4
October 6, 2005
VSC8115
Datasheet
E
LECTRICAL
S
PECIFICATIONS
DC Characteristics
Guaranteed over recommended operating conditions listed in
Table 8
on page 5.
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Table 2. LVPECL Single-Ended Inputs and Outputs
Symbol
V
IH
V
IL
I
IH
I
IL
V
OL
V
OH
Parameter
Input HIGH voltage
Input LOW voltage
Input HIGH current
Input LOW current
Output LOW voltage
Output HIGH voltage
Minimum
V
DD
– 1.125
V
DD
– 2.0
–0.5
–0.5
V
DD
– 2.0
V
DD
– 1.25
Maximum
V
DD
– 0.5
V
DD
– 1.5
10
10
V
DD
– 1.8
V
DD
– 0.67
Unit
V
V
µA
µA
V
V
Condition
Guaranteed input HIGH voltage
Guaranteed input LOW voltage
V
IN
= V
DD
– 0.5 V
V
IN
= V
DD
– 2.0 V
50Ω to (V
DD
– 2.0 V)
50Ω to (V
DD
– 2.0 V)
Table 3. LVPECL Differential Inputs
Symbol
V
IH
V
IL
∆V
IN
I
IH
I
IL
Parameter
Input HIGH voltage
Input LOW voltage
Differential input voltage
Input HIGH current
Input LOW current
Minimum
V
DD
– 1.75
V
DD
– 2.0
250
–0.5
–0.5
10
10
Maximum
V
DD
– 0.4
V
DD
– 0.7
Unit
V
V
mV
µA
µA
∆V
IN
= 0.5 V
∆V
IN
= 0.5 V
Condition
Guaranteed input HIGH voltage
Guaranteed input LOW voltage
Table 4. LVDS Differential Outputs
Symbol
V
OCM
∆V
OUT
Parameter
Output common-mode voltage
Differential output swing
Minimum
1.0
700
Typical
1.35
Maximum
1.7
1700
Unit
V
mV
Condition
Table 5. LVPECL Differential Outputs
Symbol
V
OCM
∆V
OUT
Parameter
Output Common-Mode Voltage
Differential Output Swing
Minimum
0.8
800
Typical
1.35
Maximum
1.7
1700
Unit
V
mV
Condition
50
Ω
to (V
DD
– 2.0 V)
50
Ω
to (V
DD
– 2.0 V)
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G52272 Revision 4.4
October 6, 2005
VSC8115
Datasheet
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Table 6. LVTTL Inputs
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH voltage
Input LOW voltage
Input HIGH current
Input LOW current
Minimum
2.0
0
–50
–50
Maximum
V
DD
0.8
50
50
Unit
V
V
µA
µA
V
IN
= 2.75 V, V
DD
= maximum
V
IN
= 0.5 V, V
DD
= maximum
Condition
Table 7. Power Supply Requirements
Symbol
I
DD
P
D
Parameter
Power supply current from V
DD
Power dissipation
Minimum
Typical
57
188.1
Maximum
80
277
Unit
mA
mW
Condition
Outputs unterminated
Outputs unterminated
Operating Conditions
Table 8. Recommended Operating Conditions
Symbol
V
DD
T
Parameter
Power supply voltage
Operating temperature under bias
(1)
VSC8115, VSC8115-T
VSC8115-02
VSC8115-03
Minimum
3.135
0
–40
–20
Typical
3.3
Maximum
3.465
70
85
85
Unit
V
°C
°C
°C
1.
Lower limit of specification is ambient temperature, and upper limit is case temperature.
Maximum Ratings
Table 9. Absolute Maximum Ratings
Symbol
V
DD
Parameter
Power supply voltage, referenced to GND
DC input voltage (LVPECL, LVTTL)
Output current (LVDS or LVPECL)
T
S
V
ESD
Storage temperature
Electrostatic discharge voltage, human body model
Minimum
–0.5
–0.5
+50
–65
–750
Maximum
4.0
V
DD
+ 0.5
–50
150
750
°C
V
Unit
V
V
Stresses listed under Absolute Maximum Ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values
listed is not implied. Exposure to these values for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE
This device can be damaged by ESD. Vitesse recommends that all integrated circuits
be handled with appropriate precautions. Failure to observe proper handling and
installation procedures may adversely affect reliability of the device.
