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VSKT10504

ADD-A-PAK Generation VII Power Modules Thyristor/Diode

厂商名称:Vishay(威世)

厂商官网:http://www.vishay.com

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VSKT105.., VSKH105.., VSKL105.., VSKN105.. Series
www.vishay.com
Vishay Semiconductors
ADD-A-PAK Generation VII Power Modules
Thyristor/Diode and Thyristor/Thyristor, 105 A
FEATURES
• High voltage
• Industrial standard package
• Low thermal resistance
• UL approved file E78996
• Designed and qualified for industrial level
• Material categorization: For definitions of compliance
please see
www.vishay.com/doc?99912
ADD-A-PAK
BENEFITS
PRODUCT SUMMARY
I
T(AV)
or I
F(AV)
Type
105 A
Modules - Thyristor, Standard
• Excellent thermal performances obtained by the usage of
exposed direct bonded copper substrate
• Up to 1600 V
• High surge capability
MECHANICAL DESCRIPTION
The ADD-A-PAK Generation VII, new generation of
ADD-A-PAK module, combines the excellent thermal
performances obtained by the usage of exposed direct
bonded copper substrate, with advanced compact simple
package solution and simplified internal structure with
minimized number of interfaces.
• Easy mounting on heatsink
ELECTRICAL DESCRIPTION
These modules are intended for general purpose high
voltage applications such as high voltage regulated power
supplies, lighting circuits, temperature and motor speed
control circuits, UPS and battery charger.
MAJOR RATINGS AND CHARACTERISTICS
SYMBOL
I
T(AV)
or I
F(AV)
I
O(RMS)
I
TSM,
I
FSM
I
2
t
I
2
t
V
RRM
T
Stg
T
J
Range
CHARACTERISTICS
85 °C
As AC switch
50 Hz
60 Hz
50 Hz
60 Hz
VALUES
105
235
2000
2094
20
18.26
200
400 to 1600
-40 to 130
-40 to 130
kA
2
s
kA
2
s
V
°C
A
UNITS
Revision: 14-Jan-14
Document Number: 94628
1
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VSKT105.., VSKH105.., VSKL105.., VSKN105.. Series
www.vishay.com
ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
TYPE NUMBER
VOLTAGE
CODE
04
06
08
VSK.105
10
12
14
16
V
RRM
, MAXIMUM
REPETITIVE PEAK
REVERSE VOLTAGE
V
400
600
800
1000
1200
1400
1600
V
RSM
, MAXIMUM
NON-REPETITIVE PEAK
REVERSE VOLTAGE
V
500
700
900
1100
1300
1500
1700
V
DRM
, MAXIMUM REPETITIVE
PEAK OFF-STATE VOLTAGE,
GATE OPEN CIRCUIT
V
400
600
800
1000
1200
1400
1600
20
I
RRM,
I
DRM
AT 130 °C
mA
Vishay Semiconductors
ON-STATE CONDUCTION
PARAMETER
Maximum average on-state current (thyristors)
Maximum average forward current (diodes)
Maximum continuous RMS on-state current,
as AC switch
SYMBOL
I
T(AV)
I
F(AV)
I
O(RMS)
t = 10 ms
Maximum peak, one-cycle non-repetitive
on-state or forward current
I
TSM
or
I
FSM
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
Maximum I
2
t for fusing
I
2
t
t = 8.3 ms
t = 10 ms
t = 8.3 ms
Maximum I
2
t
for fusing
Maximum value or threshold voltage
Maximum value of on-state
slope resistance
Maximum peak on-state or forward voltage
Maximum non-repetitive rate of rise of
turned on current
Maximum holding current
Maximum latching current
Notes
(1)
I
2
t for time t = I
2
t
x
t
x
x
(2)
Average power = V
2
T(TO)
x I
T(AV)
+ r
t
x (I
T(RMS)
)
(3)
16.7 % x
x I
AV
< I <
x I
AV
(4)
I >
x I
AV
I
2
t
(1)
V
T(TO)
r
t
(2)
(2)
TEST CONDITIONS
180° conduction, half sine wave,
T
C
= 85 °C
or
VALUES
105
UNITS
I
(RMS)
I
(RMS)
235
A
2000
No voltage
reapplied
100 % V
RRM
reapplied
No voltage
reapplied
100 % V
RRM
reapplied
Sinusoidal
half wave,
initial T
J
= T
J
maximum
2094
1682
1760
20
Initial T
J
= T
J
maximum
18.26
14.14
12.91
200
0.98
1.12
2.7
2.34
1.8
150
250
400
kA
2
s
t = 0.1 ms to 10 ms, no voltage reapplied
T
J
= T
J
maximum
Low level
(3)
High level
(4)
Low level
(3)
High level
(4)
I
TM
=
x I
T(AV)
I
FM
=
x I
F(AV)
T
J
= T
J
maximum
T
J
= T
J
maximum
T
J
= 25 °C
kA
2
s
V
m
V
TM
V
FM
dI/dt
I
H
I
L
V
A/μs
T
J
= 25 °C, from 0.67 V
DRM
,
I
TM
=
x I
T(AV)
, I
g
= 500 mA, t
r
< 0.5 μs, t
p
> 6 μs
T
J
= 25 °C, anode supply = 6 V,
resistive load, gate open circuit
T
J
= 25 °C, anode supply = 6 V, resistive load
mA
Revision: 14-Jan-14
Document Number: 94628
2
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VSKT105.., VSKH105.., VSKL105.., VSKN105.. Series
www.vishay.com
Vishay Semiconductors
TRIGGERING
PARAMETER
Maximum peak gate power
Maximum average gate power
Maximum peak gate current
Maximum peak negative gate voltage
SYMBOL
P
GM
P
G(AV)
I
GM
- V
GM
T
J
= -40 °C
Maximum gate voltage required to trigger
V
GT
T
J
= 25 °C
T
J
= 125 °C
T
J
= -40 °C
Maximum gate current required to trigger
I
GT
V
GD
I
GD
T
J
= 25 °C
T
J
= 125 °C
Maximum gate voltage that will not trigger
Maximum gate current that will not trigger
T
J
= 125 °C, rated V
DRM
applied
T
J
= 125 °C, rated V
DRM
applied
Anode supply = 6 V
resistive load
Anode supply = 6 V
resistive load
TEST CONDITIONS
VALUES
12
3
3
10
4.0
2.5
1.7
270
150
80
0.25
6
V
mA
mA
V
UNITS
W
A
BLOCKING
PARAMETER
Maximum peak reverse and off-state
leakage current at V
RRM
, V
DRM
Maximum RMS insulation voltage
Maximum critical rate of rise of off-state voltage
SYMBOL
I
RRM,
I
DRM
V
INS
dV/dt
TEST CONDITIONS
T
J
= 130 °C, gate open circuit
50 Hz
T
J
= 130 °C, linear to 0.67 V
DRM
VALUES
20
3000 (1 min)
3600 (1 s)
1000
UNITS
mA
V
V/μs
THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER
Junction operating temperature range
Storage temperature range
Maximum internal thermal resistance,
junction to case per leg
Typical thermal resistance,
case to heatsink per module
to heatsink
Mounting torque ± 10 %
busbar
Approximate weight
Case style
JEDEC
®
SYMBOL
T
J
T
Stg
R
thJC
R
thCS
DC operation
Mounting surface flat, smooth and greased
A mounting compound is recommended and
the torque should be rechecked after a period
of 3 hours to allow for the spread of the
compound.
TEST CONDITIONS
VALUES
- 40 to 130
0.22
°C/W
0.1
4
Nm
3
75
2.7
g
oz.
UNITS
°C
AAP GEN VII (TO-240AA)
R
CONDUCTION PER JUNCTION
DEVICES
VSK.105..
SINE HALF WAVE CONDUCTION
180°
0.04
120°
0.048
90°
0.063
60°
0.085
30°
0.125
180°
0.033
RECTANGULAR WAVE CONDUCTION
120°
0.052
90°
0.067
60°
0.088
30°
0.127
UNITS
°C/W
Note
• Table shows the increment of thermal resistance R
thJC
when devices operate at different conduction angles than DC
Revision: 14-Jan-14
Document Number: 94628
3
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VSKT105.., VSKH105.., VSKL105.., VSKN105.. Series
www.vishay.com
Vishay Semiconductors
260
240
220
200
180
160
140
120
100
80
60
40
20
0
0
Maximum average on-state power loss (W)
Maximum allowable case temperature (°C)
130
RthJC (DC) = 0.22°C/W
120
110
100
90
80
70
0
20
40
60
80
100
120
Average on-state current (A)
180°
120°
90°
60°
30°
180°
120°
90°
60°
30°
DC
RMS limit
Per leg, Tj = 130°C
20 40 60 80 100 120 140 160 180
Average on-state current (A)
Fig. 1 - Current Ratings Characteristics
Fig. 4 - On-State Power Loss Characteristics
Maximum allowable case temperature (°C)
130
120
110
100
90
80
70
0
20 40 60 80 100 120 140 160 180
Average on-state current (A)
DC
180°
120°
90°
60°
30°
1800
Peak half sine wave on-state current (A)
RthJC (DC) = 0.22°C/W
1600
At any rated load condition and with
rated Vrrm applied following surge
Initial Tj = Tj max
@ 60 Hz 0.0083 s
@ 50 Hz 0.0100s
1400
1200
1000
Per leg
800
1
10
100
Number of equal amplitude half cycle current pulses (N)
Fig. 2 - Current Ratings Characteristics
Fig. 5 - Maximum Non-Repetitive Surge Current
Maximum average on-state power loss (W)
200
180
160
140
120
100
80
60
40
20
0
0
20
40
60
80
100
120
Average on-state current (A)
Per leg, Tj = 130°C
2000
180°
120°
90°
60°
30°
Peak half sine wave on-state current (A)
1800
1600
1400
1200
1000
800
0.01
RMS limit
Maximum Non-repetitive Surge Current
Versus Pulse Train Duration. Control
of conduction may not be maintained.
Initial Tj = 130°C
No Voltage Reapplied
Rated Vrrm reapplied
Per leg
0.1
Pulse train duration (s)
1
Fig. 3 - On-State Power Loss Characteristics
Fig. 6 - Maximum Non-Repetitive Surge Current
Revision: 14-Jan-14
Document Number: 94628
4
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VSKT105.., VSKH105.., VSKL105.., VSKN105.. Series
www.vishay.com
400
Maximum total on-state power loss (W)
Vishay Semiconductors
RthSA = 0.1 °C/W
0.2 °C/W
0.3 °C/W
0.5 °C/W
0.7 °C/W
1 °C/W
2°C/W
350
300
250
200
150
100
50
0
0
40
80
180°
120°
90°
60°
30°
VSK.105 Series
Per module
Tj = 130°C
120
160
200
240
0
20
40
60
80
100 120 140
Total RMS output current (A)
Maximum allowable ambient temperature (°C)
Fig. 7 - On-State Power Loss Characteristics
700
Maximum total power loss (W)
600
500
400
300
200
100
0
0
40
180°
(sine)
180°
(rect)
RthSA = 0.1 °C/W
0.2 °C/W
0.3 °C/W
0.5 °C/W
0.7 °C/W
1 °C/W
2 °C/W
2 x VSK.105 Series
single phase bridge connected
Tj = 130°C
80
120
160
200
0
20
40
60
80
100 120 140
Total output current (A)
Maximum allowable ambient temperature (°C)
Fig. 8 - On-State Power Loss Characteristics
900
Maximum total power loss (W)
800
700
600
500
400
300
200
100
0
0
40
80
120
160
200
240
20
0
3 x VSK.105 Series
three phase bridge connected
Tj = 130°C
RthSA = 0.1 °C/W
0.2 °C/W
0.3 °C/W
0.5 °C/W
1 °C/W
120°
(rect)
40
60
80
100 120 140
Total output current (A)
Maximum allowable ambient temperature (°C)
Fig. 9 - On-State Power Loss Characteristics
Revision: 14-Jan-14
Document Number: 94628
5
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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