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VV-701-EAT-KNAE-12M3520000_SNPBDIP

CMOS Output Clock Oscillator, 12.352MHz Nom,

器件类别:无源元件    振荡器   

厂商名称:Vectron International, Inc.

厂商官网:http://www.vectron.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Vectron International, Inc.
包装说明
DILCC6,.2
Reach Compliance Code
compliant
最大控制电压
3 V
最小控制电压
0.3 V
最长下降时间
5 ns
频率调整-机械
NO
频率偏移/牵引率
50 ppm
JESD-609代码
e0
线性度
5%
安装特点
SURFACE MOUNT
端子数量
6
标称工作频率
12.352 MHz
最高工作温度
70 °C
最低工作温度
振荡器类型
CMOS
输出负载
15 pF
封装等效代码
DILCC6,.2
物理尺寸
7.0mm x 5.0mm x 1.6mm
最长上升时间
5 ns
最大供电电压
3.465 V
最小供电电压
3.135 V
标称供电电压
3.3 V
表面贴装
YES
最大对称度
55/45 %
端子面层
Tin/Lead (Sn/Pb)
文档预览
VV-701
Voltage Controlled Crystal Oscillator
Previous Vectron Model VVC1/VVC2
VV-701
Description
Vectron’s VV-701 Voltage Controlled Crystal Oscillator (VCXO) is a quartz stabilized square wave generator with a CMOS output. The VV-701 uses
fundamental crystals resulting in low jitter performance and a monolithic IC which improves reliability and
reduces cost.
Features
CMOS output VCXO
Output Frequencies from 1.544 MHz to 77.760 MHz
5.0 or 3.3 V Operation
High Impedance Control Voltage Option
Fundamental Crystal Design with Low Jitter Performance
Output Disable Feature
Excellent 20ppm Temperature Stability,
0/70°C or -40/85°C Operating Temperature
Small Industry Standard Package, 5.0x7.0x1.8mm
Product is free of lead and compliant to EC RoHS Directive
Applications
SONET/SDH/DWDM
Ethernet, SynchE
xDSL, PCMIA
Digital Video
Broadband Access
Base Stations, Picocells
Block Diagram
V
DD
E/D or NC
Output
Crystal
Oscillator
V
C
E/D or NC
Page1
Gnd
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Performance Specifications
Table 1. Electrical Performance
Performance Specifications
Parameter
Voltage
1
, 5V option
3.3V option
Current
2
, 5V option, 1.544-30MHz
30.001-50.000
50.001-77.760MHz
3.3V option, 1.544-30MHz
30.001-50.000
50.001-77.760MHz
Nominal Frequency
3
Pull Range
2,6
,
ordering option
Linearity
2
Gain Transfer
2
Temperature Stability
Output Logic Levels
2
Output Logic High
Output Logic Low
Load
Rise Time
2,4
Fall Time
2,4
Symmetry
2
Period Jitter
5,7
, RMS (61.44 MHz)
Peak-Peak (61.440MHz)
Jitter
8
, 12kHz-20MHz (61.44 MHz)
Phase Noise
8,
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Control Voltage
Control Voltage Range for Pull Range
Control Voltage Input Impedance
“E” Ordering option
Control Voltage Modulation BW
Output Enable/Disable
9
Output Enabled
Output Disabled
Start-Up Time
Operating Temp,
ordering option
Package Size
1]
2]
3]
4]
5]
6]
7]
8]
9]
Symbol
V
DD
I
DD
Min
Supply
4.750
3.135
Typical
5.0
3.3
Maximum
5.250
3.465
10
12
18
5
9
14
Units
V
mA
Frequency
f
N
APR
TPR
Lin
K
V
f
STAB
Outputs
V
0.9*V
DD
0.1*V
DD
I
OUT
t
R
t
F
SYM
фJ
фJ
45
50
3.0
23
90
-63
-97
-129
-144
-157
-159
-164
V
C
Z
IN
2
BW
10
0.9*V
DD
0.1*V
DD
10
T
OP
0/70 or -40/85
5.0 x 7.0 x 1.8
ms
°C
mm
0.5
0.3
100
4.5
3.0
15
5
5
55
pF
ns
ns
%
ps
fs
dBc/Hz
1.544
±50, ±80, ±100
±50, ±100, ±150
5
Positive, +65
±20
77.760
MHz
ppm
%
ppm/V
ppm
V
KΩ
kHz
V
The power supply should have by-pass capacitors as close to the supply and to ground as possible, for examples 0.1 and 0.01uF
Parameters are tested with production test circuit (Fig 1).
See Standard Frequencies and Ordering Information tables for more specific information
Measured from 20% to 80% of a full output swing (Fig 2).
Not tested in production, guaranteed by design, verified at qualification.
Tested with Vc = 0.3V to 3.0V unless otherwise stated in part description
Broadband Period Jitter measured using Wavecrest SIA3300C, 90K samples, see Application Note for Typical Phase Noise and Jitter Performance
Phase Noise is measured with an Agilent E5052A, see Application Note for Typical Phase Noise and Jitter Performance
The Output is Enabled if the Enable/Disable is left open.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page2
Test Circuit
Waveform
I
DD
0.8*V
DD
6
+
V
DD
-
.1µF
I
C
V
C
1
+
-
4
50%
3
15pF
0.1*V
DD
t
R
t
F
On Time
Period
Fig 1: Test Circuit
Table 2. Absolute Maximum Ratings
Parameter
Power Supply
Voltage Control Range
Storage Temperature
Soldering Temp/Time
Fig 2: Output Waveform
Symbol
V
CC
V
C
TS
T
LS
Ratings
0 to 6
0 to V
CC
-55 to 125
260 / 20
Unit
V
V
°C
°C / sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or
any other conditions in excess of conditions represented in the operational sections of this datasheet. Exposure to absolute maximum
ratings for extended periods may adversely affect device reliability. Permanent damage is also possible if OD or Vc is applied before Vcc.
Typical Phase Noise
Typical Gain
VV-701 @ 61.44 MHz
150
100
90
100
80
70
50
60
Vc (volts)
0
0
0.5
1
1.5
2
2.5
3
40
-50
30
50
Gain (ppm/V)
Pull (ppm)
Pull
Gain
20
-100
10
-150
0
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page3
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow
simulation. The VV-701 family is capable of meeting the following qualification tests:
Table 3. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Moisture Sensitivity Level
Contact Pads
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2015
MSL 1
Gold over Nickel
Handling Precautions
Although ESD protection circuitry has been designed into the VV-701 proper precautions should be taken when handling and
mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing and design
protection evaluation.
Table 4. ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
500V
500V
Conditions
MIL-STD-883, Method 3015
JESD22-C101
Table 5. Reflow Profile
Parameter
PreHeat Time
Ts-min
Ts-max
Ramp Up
Time Above 217 °C
Time To Peak Temperature
Time at 260 °C
Ramp Down
Symbol
t
S
Value
60 sec Min, 260 sec Max
150°C
200°C
3 °C/sec Max
60 sec Min, 150 sec Max
480 sec Max
30 sec Max
6 °C/sec Max
R
UP
t
L
T
25C to peak
t
P
R
DN
The device is qualified to meet the JEDEC
standard for Pb-Free assembly. The
temperatures and time intervals listed are
based on the Pb-Free small body requirements.
The VV-701 device is hermetically sealed so an
aqueous wash is not an issue.
Termination Plating:
Electroless Gold Plate over Nickel Plate
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page4
Outline Drawing & Pad Layout
1.96
VV-XXX
XXMXXX
YYWW C
#4
#3
#5
#6
Bottom View
#2
#1
1.78
3.66
1.6±0.12
2.54
Dimensions in inches (mm)
5.08
Table 6. Pin Out
Pin
1
2
3
4
5
6
Symbol
V
C
E/D
GND
Output
E/D
Function
VCXO Control Voltage
Enable Disable or NC
Case and Electrical Ground
Output
Enable Disable or NC
Power Supply Voltage
V
DD
Tape & Reel (EIA-481-2-A)
Table 7. Tape and Reel Information
Tape Dimensions (mm)
Dimension
Tolerance
VV-701
Reel Dimensions (mm)
Po
Typ
4
W
Typ
12
F
Typ
5.5
Do
Typ
1.5
P1
Typ
8
A
Typ
178
B
Min
1.78
C
Typ
13
D
Min
20.6
N
Min
55
W1
Typ
12.4
W2
Max
22.4
# Per
Reel
500
Page5
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