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VX-721-HAE-KEAN-322M265650

LVCMOS Output Clock Oscillator

器件类别：无源元件    振荡器   

厂商名称：Vectron International, Inc.

厂商官网：http://www.vectron.com/

器件标准：  

下载文档
参数 预览
器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
Objectid
1261412937
Reach Compliance Code
compliant
其他特性
ENABLE/DISABLE FUNCTION; TR, 7 INCH
最大控制电压
2.5 V
最小控制电压
最长下降时间
1.2 ns
频率调整-机械
NO
频率偏移/牵引率
50 ppm
频率稳定性
20%
JESD-609代码
e4
线性度
10%
安装特点
SURFACE MOUNT
标称工作频率
322.26565 MHz
最高工作温度
85 °C
最低工作温度
-40 °C
振荡器类型
LVCMOS
输出负载
15 pF
物理尺寸
7.0mm x 5.0mm x 1.62mm
最长上升时间
1.2 ns
最大供电电压
2.75 V
最小供电电压
2.25 V
标称供电电压
2.5 V
表面贴装
YES
最大对称度
55/45 %
端子面层
Gold (Au) - with Nickel (Ni) barrier
文档预览
Single Frequency HPLL VCXO
VX-721
VX-721
Features
Description
Applications
The VX-721 is a voltage controlled crystal oscillator, VCXO, based upon Vectron’s HPLL high performance phase locked loop frequency
multiplier ASIC that combines key digital synthesis techniques with VI’s proven core analog technology blocks. A standard low frequency
crystal provides the reference to the fractional-n synthesizer so that virtually any frequency between 10MHz and 1200 MHz can be factory
programmed allowing quick turn manufacturing.
Features
• Industry Standard Package, 5.0 x 7.0 x 1.8 mm
• HPLL High Performance PLL ASIC
• Jitter < 500 fs-rms (12 kHz to 20 MHz)
• Output Frequencies from 10 MHz to 1200 MHz
• Spurious Suppression, 70 dBc Typical
• 2.5V or 3.3V Supply Voltage
• LVCMOS, LVPECL or LVDS Output Configurations
• Output Enable
• Compliant to EC RoHS Directive
Applications
PLL circuits for clock smoothing and frequency translation
Description
Standard
• 1-2-4 Gigabit Fibre Channel
• 10 Gigabit Fibre Channel
• 10GbE LAN / WAN
• Synchronous Ethernet
• OC-192
• SONET / SDH
INCITS 352-2002
INCITS 364-2003
IEEE 802.3ae
ITU-T G.8262
ITU-T G.709
GR-253-CORE Issue4
Block Diagram
V
DD
COutput
Output
XTAL
LVCMOS
LVPECL
LVDS
HPLL
Vc
OE
Figure 1 - Block Diagram
Gnd
Page 1 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev2: 14 November 2012
VX-721 Single Frequency HPLL VCXO
Performance Specifications
Electrical Performance
Parameter
Voltage
1
Current
Test Conditions
3.3V Option
2.5V Option
LVCMOS
LVPECL
Symbol
Supply
V
DD
I
DD
T
OP
Min
2.97
2.25
-
-
-
-40
0.75 x V
DD
-
Typ
3.3
2.5
90
99
120
-
-
-
-
-
-
-
+100
±20
Max
3.63
2.75
98
108
130
+85
-
0.5
1200
160
-
±10
-
-
V
DD
-1.25
1.9
1.8
600
V
DD
0.1 x V
DD
350
1.2
55
-
1000
500
-
-
V
DD
Units
V
LVDS
mA
°C
V
Operating Temperature
1, 3
Output Enable (OE)
V
IH
V
IL
Frequency
Nominal Frequency
1
Absolute Pull Range
1, 2, 3
Linearity
2, 4
Gain Transfer
2,
Temperature Stability
1, 6
LVPECL Output
LVDS Output
LVCMOS Output
LVPECL/LVDS
LVCMOS
V
C
= 0.1xV
DD
to 0.9xV
DD
20% to 80% full output
10 to 90% of V
DD
T
A
= -40 to +85°C
mid-level
swing (diff )
mid-level
swing (diff )
f
N
APR
Lin
10
10
±50
-
-
-
V
DD
-1.42
1.1
1.4
300
0.9 x V
DD
-
-
-
45
65
MHz
ppm
%
ppm/V
ppm
V
V
PP
V
mV
PP
V
V
ps
ns
%
dBc
fs-rms
fs-rms
kΩ
kHz
V
K
V
f
STAB
Outputs
V
O
V
OD
V
O
V
OD
V
OH
V
OL
-
-
1.6
450
-
-
-
-
50
70
-
-
-
10.0
-
Rise/Fall Time (20/80%)
2,5
Symmetry
2,3
LVPECL/LVDS
LVCMOS with C
L
= 15 pF
LVPECL: V
DD
-1.3 V (diff )
LVDS: 1.6 V (diff )
LVCMOS: V
DD
/2
12 kHz to 20 MHz
12 kHz to 20 MHz
t
R/
t
f
SYM
Spurious Suppression
6
Jitter
6
(Performance Option N)
Jitter
6
(Performance Option A)
Input Impedance (Output Enabled)
6
Modulation Bandwidth
Control Voltage Tuning Range
1]
2]
3]
4]
5]
6]
фJ
фJ
-
-
500
-
0
Control Voltage
Z
C
BW
V
C
See Standard Frequencies and Ordering Information (Pg 8).
Parameters are tested with production test circuit (See Figure 2 for LVCMOS, Figure 3 for LVPECL and figure 4 for LVDS).
Parameters are tested at ambient temperature with test limits guard-banded for specified operating temperature.
Measured as the maximum deviation from the best straight-line fit, per MIL-0-55310.
Parameters are described with waveform diagram below (Figure 5).
Not tested in production, guaranteed by design, verified at qualification.
Page 2 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev2: 14 November 2012
VX-721 Single Frequency HPLL VCXO
Test Circuits & Output Waveform
+3.3V
VC
10nF
1nF
VC
+3.3V
10nF
1nF
1
6
1
6
OE
2
5
NC
39
10nF
Scope
OE
2
5
10nF
Scope
3
4
3
4
200
200
10k
10k
10nF
10k
10nF
VMD
VMD
10nF
Figure 2 - LVCMOS Production Test Circuit
Figure 3 - LVPECL Production Test Circuit
+3.3V
VC
10nF
1nF
t
R
10nF
Scope
t
F
1
6
OE
2
5
80
%
3
4
10k
10k
10nF
Vs
20
%
On Time
10nF
VMD
Period
Figure 4 - LVDS Production Test Circuit
Figure 5 - Waveform Diagram
Absolute Maximum Ratings
Parameter
Power Supply
Input Current
Output Current
Voltage Control Range
Output Enable
Storage Temperature
Soldering Temperature / Duration
Symbol
V
DD
I
IN
I
OUT
V
C
OE
T
STR
T
PEAK
/ t
P
Ratings
0 to 3.8
100
25
0 to V
DD
0 to V
DD
-55 to 125
260 / 40
Unit
V
mA
mA
V
V
°C
°C / sec
Page 3 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev2: 14 November 2012
VX-721 Single Frequency HPLL VCXO
LVPECL Application Diagrams
+3.3V
VC
10nF
1nF
1
6
10nF
OE
2
5
10nF
3
4
240
240
3
4
82
82
OE
2
5
10nF
1
6
130
130
10nF
VC
+3.3V
10nF
+3.3V
1nF
Figure 6 - Single Resistor Termination Scheme
Resistor values are typically 120 to 240 ohms for 3.3V operation and 82 to 120 ohms for 2.5V
operation.
Figure 7 - Pull Up Pull Down Termination
Resistor values are typically for 3.3V operation
For 2.5V operation, the resistor to ground is 62 ohms and the resistor to supply is 240 ohms
There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 6,
and a pull-up/pull-down scheme as shown in Figure 7. An AC coupling capacitor is optional, depending on the application and the input logic requirements of
the next stage.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-
terminated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
LVDS Application Diagrams
+3.3V
VC
10nF
1nF
1
6
Receiver
100
3
4
3
4
1
6
10nF
100
Receiver
VC
+3.3V
10nF
1nF
OE
2
5
OE
2
5
10nF
Figure 8 - LVDS to LVDS, internal 100Ω
Some LVDS structures have an internal 100 ohm resistor on the
input and do not need additional components.
Figure 9 - LVDS to LVDS, External 100Ω and AC block ing caps
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-
terminated, and if one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
Page 4 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev2: 14 November 2012
VX-721 Single Frequency HPLL VCXO
Typical Characteristics
Figure 10 - Typical Phase Noise/Jitter Performance - INTEGER Mode
Figure 11 - Typical VC Pull
Page 5 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev2: 14 November 2012
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器件捷径:
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