W24512A
64K
×
8 HIGH SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W24512A is a high speed, low power CMOS static RAM organized as 65536
×
8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
•
High speed access time: 25 nS (max.)
Low power consumption:
−
Active: 800 mW (max.)
Single +5V power supply
Fully static operation
•
•
•
All inputs and outputs directly TTL compatible
Three-state outputs
Available packages: 32-pin 300 mil SOJ, 450
mil SOP, and standard type one TSOP
(8 mm
×
20 mm)
•
•
PIN CONFIGURATIONS
BLOCK DIAGRAM
V
DD
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O 1
I/O 2
I/O 3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A1 0
CS1
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
V
SS
A0
.
.
A15
DECODER
CORE
ARRAY
CS2
CS1
OE
WE
CONTROL
DATA I/O
I/O1
.
.
I/O8
PIN DESCRIPTION
SYMBOL
A0−A15
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
A3
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A11
A9
A8
A13
WE
CS2
A15
V
DD
NC
NC
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O1−I/O8
CS1, CS2
WE
OE
V
DD
V
SS
NC
32-pin
TSOP
-1-
Publication Release Date: April 1997
Revision A3
W24512A
TRUTH TABLE
CS1
H
X
L
L
L
CS2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
MODE
Not Selected
Not Selected
Output Disable
Read
Write
I/O1−I/O8
High Z
High Z
High Z
Data Out
Data In
V
DD
CURRENT
I
SB
, I
SB1
I
SB
, I
SB1
I
DD
I
DD
I
DD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to V
SS
Potential
Input/Output to V
SS
Potential
Allowable Power Dissipation
Storage Temperature
Operating Temperature
RATING
-0.5 to +7.0
-0.5 to V
DD
+0.5
1.0
-65 to +150
0 to +70
UNIT
V
V
W
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(V
DD
= 5V
±10%,
V
SS
= 0V, T
A
= 0 to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage
Current
SYM.
V
IL
V
IH
I
LI
I
LO
TEST CONDITIONS
-
-
V
IN
= V
SS
to V
DD
V
I/O
= V
SS
to V
DD
CS1 = V
IH (min.)
or
CS2 = V
IL (max.)
or
OE = V
IH (min.)
or
WE = V
IL (max.)
I
OL
= +8.0 mA
I
OH
= -4.0 mA
CS1 = V
IL (max.)
,
CS2 = V
IH (min.)
I/O = 0mA, Cycle = min
Duty = 100%
CS1 = V
IH (min.)
or
CS2 = V
IL (max.)
Cycle = min, Duty = 100%
CS1
≥
V
DD
-0.2V or
CS2
≤
0.2V
MIN.
-0.5
+2.2
-10
-10
TYP.
-
-
-
-
MAX.
+0.8
V
DD
+0.5
+10
+10
UNIT
V
V
µA
µA
Output Low Voltage
Output High Voltage
Operating Power
Supply Current
V
OL
V
OH
I
DD
-
2.4
-
-
-
-
0.4
-
160
V
V
mA
Standby Power
Supply Current
I
SB
-
-
30
mA
I
SB1
-
-
10
mA
Note: Typical characteristics are at V
DD
= 5V, T
A
= 25° C.
-2-
W24512A
CAPACITANCE
(V
DD
= 5V, T
A
= 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
C
IN
C
I/O
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
8
10
UNIT
pF
pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
0V to 3V
5 nS
1.5V
C
L
= 30 pF, I
OH
/I
OL
= -4 mA/8 mA
CONDITIONS
AC Test Loads and Waveform
R1 480 ohm
R1 480 ohm
5V
OUTPUT
OUTPUT
30 pF
Including
Jig and
Scope
5V
5 pF
R2
255 ohm
Including
Jig and
Scope
R2
255 ohm
(For T
CLZ1,
T
CLZ2,
T
OLZ,
T
CHZ1,
T
CHZ2,
T
OHZ,
T
WHZ,
T
OW
)
3.0V
90%
10%
5 nS
10%
90%
0V
5 nS
-3-
Publication Release Date: April 1997
Revision A3
W24512A
AC Characteristics,continued
(V
DD
= 5V
±10%,
V
SS
= 0V, T
A
= 0 to 70° C)
Read Cycle
PARAMETER
Read Cycle Time
Address Access Time
Chip Select Access Time
CS1
CS2
Output Enable to Output Valid
Chip Selection to Output in Low Z
CS1
CS2
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
CS1
CS2
Output Disable to Output in High Z
Output Hold from Address Change
*
These parameters are sampled but not 100% tested.
SYM.
T
RC
T
AA
T
ACS1
T
ACS2
T
AOE
T
CLZ1
*
T
CLZ2
*
T
OLZ
*
T
CHZ1
*
T
CHZ2
*
T
OHZ*
T
OH
W24512A-25
MIN.
25
-
-
-
-
3
3
0
-
-
-
3
MAX.
-
25
25
25
12
-
-
-
12
12
12
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
UNIT
Write Cycle
PARAMETER
Write Cycle Time
Chip Selection to End of Write
CS1
CS2
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
CS1
,
WE
CS2
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
* T
hese parameters are sampled but not 100% tested.
-4-
SYM.
T
WC
T
CW1
T
CW2
T
AW
T
AS
T
WP
T
WR1
T
WR2
T
DW
T
DH
T
WHZ
*
T
OHZ
*
T
OW
W24512A-25
MIN.
25
18
18
18
0
15
0
0
12
0
-
-
0
MAX.
-
-
-
-
-
-
-
-
-
-
12
12
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
UNIT
W24512A
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
T
RC
Address
T
AA
T
OH
T
OH
D
OUT
Read Cycle 2
(Chip Select Controlled)
CS1
T
ACS1
CS2
T
ACS2
T
CHZ2
T
CHZ1
T
CLZ1
D
OU
T
CLZ2
Read Cycle 3
(Output Enable Controlled)
T
RC
Address
T
AA
OE
T
AOE
T
OLZ
CS1
T
ACS1
T
CLZ1
CS2
T
ACS2
T
CLZ2
D
OUT
T
CHZ2
T
OHZ
T
CHZ1
T
OH
-5-
Publication Release Date: April 1997
Revision A3
