W25N01GVxxIG/IT
3V 1G-BIT
SERIAL SLC NAND FLASH MEMORY WITH
DUAL/QUAD SPI
BUFFER READ & CONTINUOUS READ
Publication Release Date: May 09, 2018
Revision L
W25N01GVxxIG/IT
Table of Contents
1.
2.
3.
GENERAL DESCRIPTIONS............................................................................................................. 6
FEATURES ....................................................................................................................................... 6
PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7
3.1
Pad Configuration WSON 8x6-mm ...................................................................................... 7
3.2
Pad Description WSON 8x6-mm .......................................................................................... 7
3.3
Pin Configuration SOIC 300-mil ........................................................................................... 8
3.4
Pin Description SOIC 300-mil ............................................................................................... 8
3.5
Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 9
3.6
Ball Description TFBGA 8x6-mm ......................................................................................... 9
PIN DESCRIPTIONS ...................................................................................................................... 10
4.1
Chip Select (/CS) ................................................................................................................ 10
4.2
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 10
4.3
Write Protect (/WP)............................................................................................................. 10
4.4
HOLD (/HOLD) ................................................................................................................... 10
4.5
Serial Clock (CLK) .............................................................................................................. 10
BLOCK DIAGRAM .......................................................................................................................... 11
FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12
6.1
Device Operation Flow ....................................................................................................... 12
6.1.1
6.1.2
6.1.3
6.1.4
Standard SPI Instructions ..................................................................................................... 12
Dual SPI Instructions ............................................................................................................ 12
Quad SPI Instructions ........................................................................................................... 13
Hold Function........................................................................................................................ 13
4.
5.
6.
7.
6.2
Write Protection .................................................................................................................. 14
PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 15
7.1
Protection Register / Status Register-1 (Volatile Writable, OTP lockable)......................... 15
7.1.1
Block Protect Bits (BP3, BP2, BP1, BP0, TB) –
Volatile Writable, OTP lockable
.................. 15
7.1.2
Write Protection Enable Bit (WP-E) –
Volatile Writable, OTP lockable
................................. 16
7.1.3
Status Register Protect Bits (SRP1, SRP0) –
Volatile Writable, OTP lockable
..................... 16
7.2
Configuration Register / Status Register-2 (Volatile Writable) ........................................... 17
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
One Time Program Lock Bit (OTP-L) –
OTP lockable
.......................................................... 17
Enter OTP Access Mode Bit (OTP-E) –
Volatile Writable
..................................................... 17
Status Register-1 Lock Bit (SR1-L) –
OTP lockable
............................................................. 17
ECC Enable Bit (ECC-E) –
Volatile Writable
......................................................................... 18
Buffer Read / Continuous Read Mode Bit (BUF) –
Volatile Writable
..................................... 18
Look-Up Table Full (LUT-F) –
Status Only
............................................................................ 19
Cumulative ECC Status (ECC-1, ECC-0) –
Status Only
....................................................... 19
Program/Erase Failure (P-FAIL, E-FAIL) –
Status Only
........................................................ 20
Write Enable Latch (WEL) –
Status Only
.............................................................................. 20
Erase/Program In Progress (BUSY) –
Status Only
............................................................... 20
Reserved Bits –
Non Functional
........................................................................................... 20
7.3
Status Register-3 (Status Only) .......................................................................................... 19
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
W25N01GV Status Register Memory Protection ............................................................... 21
-1-
W25N01GVxxIG/IT
8.
INSTRUCTIONS ............................................................................................................................. 22
8.1
Device ID and Instruction Set Tables ................................................................................. 22
8.1.1
Manufacturer and Device Identification ................................................................................. 22
8.1.2
Instruction Set Table 1 (Continuous Read, BUF = 0, xxIT Default Power Up Mode)
(11)
........ 23
8.1.3
Instruction Set Table 2 (Buffer Read, BUF = 1, xxIG Default Power Up Mode)
(12)
................ 24
8.2
Instruction Descriptions ...................................................................................................... 26
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.2.16
8.2.17
8.2.18
8.2.19
8.2.20
8.2.21
8.2.22
8.2.23
8.2.24
8.2.25
8.2.26
8.2.27
Device Reset (FFh) ............................................................................................................... 26
Read JEDEC ID (9Fh) ..........................................................................................................27
Read Status Register (0Fh / 05h) ......................................................................................... 28
Write Status Register (1Fh / 01h) ......................................................................................... 29
Write Enable (06h) ................................................................................................................ 30
Write Disable (04h) ............................................................................................................... 30
Bad Block Management (A1h) .............................................................................................. 31
Read BBM Look Up Table (A5h) .......................................................................................... 32
Last ECC Failure Page Address (A9h) ................................................................................. 33
128KB Block Erase (D8h) ................................................................................................... 34
Load Program Data (02h) / Random Load Program Data (84h) ......................................... 35
Quad Load Program Data (32h) / Quad Random Load Program Data (34h) ...................... 36
Program Execute (10h) ....................................................................................................... 37
Page Data Read (13h) ........................................................................................................ 38
Read Data (03h) ................................................................................................................. 39
Fast Read (0Bh) ................................................................................................................. 40
Fast Read with 4-Byte Address (0Ch)................................................................................. 41
Fast Read Dual Output (3Bh) ............................................................................................. 42
Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 43
Fast Read Quad Output (6Bh) ............................................................................................ 44
Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 45
Fast Read Dual I/O (BBh) ................................................................................................... 46
Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 47
Fast Read Quad I/O (EBh).................................................................................................. 48
Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................. 50
Accessing Unique ID / Parameter / OTP Pages (OTP-E=1) ............................................... 52
Parameter Page Data Definitions ....................................................................................... 53
9.
ELECTRICAL CHARACTERISTICS............................................................................................... 54
9.1
Absolute Maximum Ratings (1) .......................................................................................... 54
9.2
9.3
Operating Ranges .............................................................................................................. 54
Power-up Power-down Timing Requirements .................................................................... 55
9.3.1
Power-up Timing and Voltage Levels ................................................................................... 55
9.3.2
Power-up, Power-Down Requirement .................................................................................. 55
9.4
9.5
9.6
9.7
9.8
9.9
DC Electrical Characteristics .............................................................................................. 56
AC Measurement Conditions ............................................................................................. 57
AC Electrical Characteristics
(3)
........................................................................................... 58
Serial Output Timing ........................................................................................................... 60
Serial Input Timing.............................................................................................................. 60
/HOLD Timing ..................................................................................................................... 60
Publication Release Date: May 09, 2018
Revision L
-2-
W25N01GVxxIG/IT
9.10
/WP Timing ......................................................................................................................... 60
INVALID BLOCK MANAGEMENT .................................................................................................. 61
10.1
Invalid blocks ...................................................................................................................... 61
10.2
Initial invalid blocks ............................................................................................................. 61
PACKAGE SPECIFICATIONS ....................................................................................................... 62
11.1
8-Pad WSON 8x6-mm (Package Code ZE) ....................................................................... 62
11.2
16-Pin SOIC 300-mil (Package Code SF) .......................................................................... 63
11.3
24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array) ......................................... 64
11.4
24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 Ball Array) ............................................ 65
ORDERING INFORMATION .......................................................................................................... 66
12.1
Valid Part Numbers and Top Side Marking ........................................................................ 67
REVISION HISTORY ...................................................................................................................... 68
10.
11.
12.
13.
-3-
W25N01GVxxIG/IT
Table of Figures
Figure 1a. W25N01GV Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE) .............................. 7
Figure 1b. W25N01GV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) .................................. 8
Figure 1c. W25N01GV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC) ................... 9
Figure 2. W25N01GV Flash Memory Architecture and Addressing ........................................................... 11
Figure 3. W25N01GV Flash Memory Operation Diagram .......................................................................... 12
Figure 4a. Protection Register / Status Register-1 (Address Axh) ............................................................. 15
Figure 4b. Configuration Register / Status Register-2 (Address Bxh) ........................................................ 17
Figure 4c. Status Register-3 (Address Cxh) ............................................................................................... 19
Figure 5. Device Reset Instruction .............................................................................................................. 26
Figure 6. Read JEDEC ID Instruction ......................................................................................................... 27
Figure 7. Read Status Register Instruction ................................................................................................. 28
Figure 8. Write Status Register-1/2/3 Instruction ........................................................................................ 29
Figure 9. Write Enable Instruction ............................................................................................................... 30
Figure 10. Write Disable Instruction ............................................................................................................ 30
Figure 11. Bad Block Management Instruction ........................................................................................... 31
Figure 12. Read BBM Look Up Table Instruction ....................................................................................... 32
Figure 13. Last ECC Failure Page Address Instruction .............................................................................. 33
Figure 14. 128KB Block Erase Instruction .................................................................................................. 34
Figure 15. Load / Random Load Program Data Instruction ........................................................................ 35
Figure 16. Quad Load / Quad Random Load Program Data Instruction .................................................... 36
Figure 17. Program Execute Instruction ..................................................................................................... 37
Figure 18. Page Data Read Instruction....................................................................................................... 38
Figure 19a. Read Data Instruction (Buffer Read Mode, BUF=1) ................................................................ 39
Figure 19b. Read Data Instruction (Continuous Read Mode, BUF=0) ....................................................... 39
Figure 20a. Fast Read Instruction (Buffer Read Mode, BUF=1) ................................................................ 40
Figure 20b. Fast Read Instruction (Continuous Read Mode, BUF=0) ........................................................ 40
Figure 21a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ............................... 41
Figure 21b. Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)....................... 41
Figure 22a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1) ............................................ 42
Figure 22b. Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0) ................................... 42
Figure 23a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ........... 43
Figure 23b. Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) .. 43
Figure 24a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) ........................................... 44
Figure 24b. Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0) .................................. 44
Figure 25a. Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ......... 45
Figure 25b. Fast Read Quad Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) . 45
Figure 26a. Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1) .................................................. 46
Figure 26b. Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0).......................................... 46
Figure 27a. Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................. 47
Figure 27b. Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ........ 47
Figure 28a. Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1) ................................................. 48
Figure 28b. Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0) ........................................ 49
Publication Release Date: May 09, 2018
Revision L
-4-
分立器件
