W25Q256JW
1.8V 256M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI
Publication Release Date: September 04, 2018
- Revision D
W25Q256JW
Table of Contents
1.
2.
3.
GENERAL DESCRIPTIONS ............................................................................................................. 5
FEATURES ....................................................................................................................................... 5
PACKAGE TYPES AND PIN CONFIGURATIONS........................................................................... 6
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.
4.1
4.2
4.3
4.4
4.5
4.6
5.
6.
Pad Configuration 6x5-mm/ 8x6-mm.................................................................................... 6
Pad Description WSON 6x5-mm/ 8x6-mm .......................................................................... 6
Pin Configuration SOIC 300-mil ........................................................................................... 7
Pin Description SOIC 300-mil ............................................................................................... 7
Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8
Ball Description TFBGA 8x6-mm ......................................................................................... 8
Ball Configuration WLCSP ................................................................................................... 9
Ball Description WLCSP ....................................................................................................... 9
Chip Select (/CS) ................................................................................................................ 10
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ................................... 10
Write Protect (/WP) ............................................................................................................ 10
HOLD (/HOLD) ................................................................................................................... 10
Serial Clock (CLK) .............................................................................................................. 10
Reset (/RESET) .................................................................................................................. 10
PIN DESCRIPTIONS ...................................................................................................................... 10
BLOCK DIAGRAM .......................................................................................................................... 11
FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12
6.1
SPI Operations ................................................................................................................... 12
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Standard SPI Instructions ..................................................................................................... 12
Dual SPI Instructions ............................................................................................................ 12
Quad SPI Instructions ........................................................................................................... 12
3-Byte / 4-Byte Address Modes ............................................................................................ 13
Software Reset & Hardware /RESET pin .............................................................................. 13
6.2
7.
7.1
Write Protection .................................................................................................................. 14
Status Registers ................................................................................................................. 15
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.1
7.1.2
Erase/Write In Progress (BUSY)
–
Status Only
................................................................ 15
Write Enable Latch (WEL)
–
Status Only
.......................................................................... 15
Block Protect Bits (BP3, BP2, BP1, BP0)
–
Volatile/Non-Volatile Writable
....................... 16
Top/Bottom Block Protect (TB)
–
Volatile/Non-Volatile Writable
....................................... 16
Complement Protect (CMP)
–
Volatile/Non-Volatile Writable
............................................ 16
Status Register Protect (SRP, SRL)
–
Volatile/Non-Volatile Writable
............................... 17
Erase/Program Suspend Status (SUS)
–
Status Only.......................................................
18
STATUS AND CONFIGURATION REGISTERS ............................................................................ 15
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W25Q256JW
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
Security Register Lock Bits (LB3, LB2, LB1)
–
Volatile/Non-Volatile OTP Writable
.......... 18
Quad Enable (QE)
–
Volatile/Non-Volatile Writable
.......................................................... 18
Current Address Mode (ADS)
–
Status Only
..................................................................... 19
Power-Up Address Mode (ADP)
–
Non-Volatile Writable
.................................................. 19
Write Protect Selection (WPS)
–
Volatile/Non-Volatile Writable
....................................... 19
Output Driver Strength (DRV1, DRV0)
–
Volatile/Non-Volatile Writable
........................... 20
Reserved Bits
–
Non Functional
........................................................................................ 20
W25Q256JW Status Register Memory Protection (WPS = 0, CMP = 0) ........................... 21
W25Q256JW Status Register Memory Protection (WPS = 0, CMP = 1) ........................... 22
W25Q256JW Individual Block Memory Protection (WPS=1) ............................................. 23
7.2
8.
Extended Address Register
–
Volatile Writable Only
...................................................... 24
INSTRUCTIONS ............................................................................................................................. 25
8.1
Device ID and Instruction Set Tables ................................................................................. 25
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Manufacturer and Device Identification ................................................................................ 25
Instruction Set Table 1 (Standard/Dual/Quad SPI, 3-Byte Address Mode)
(1)
....................... 26
Instruction Set Table 2 (Dual/Quad SPI Instructions,3-Byte Address Mode) ....................... 27
Instruction Set Table 3 (Standard SPI, 4-Byte Address Mode)
(1)
.......................................... 28
Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode) ...................... 29
Write Enable (06h) ............................................................................................................... 31
Write Enable for Volatile Status Register (50h) .................................................................... 31
Write Disable (04h) ............................................................................................................... 32
Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 32
Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 33
Read Extended Address Register (C8h) .............................................................................. 35
Write Extended Address Register (C5h) .............................................................................. 36
Enter 4-Byte Address Mode (B7h) ........................................................................................ 37
Exit 4-Byte Address Mode (E9h) .......................................................................................... 37
Read Data (03h) ................................................................................................................. 38
Read Data with 4-Byte Address (13h) ................................................................................ 39
Fast Read (0Bh) ................................................................................................................. 40
Fast Read with 4-Byte Address (0Ch) ................................................................................ 41
Fast Read Dual Output (3Bh) ............................................................................................. 42
Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 43
Fast Read Quad Output (6Bh) ............................................................................................ 44
Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 45
Fast Read Dual I/O (BBh) ................................................................................................... 46
Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 47
Fast Read Quad I/O (EBh) ................................................................................................. 48
Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................ 49
Page Program (02h) ........................................................................................................... 50
8.2
Instruction Descriptions ...................................................................................................... 31
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.2.16
8.2.17
8.2.18
8.2.19
8.2.20
8.2.21
8.2.22
Figure 7. Write Disable Instruction for SPI Mode .............................................................................. 32
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Publication Release Date: September 04, 2018
- Revision D
W25Q256JW
8.2.23
8.2.24
8.2.25
8.2.26
8.2.27
8.2.28
8.2.29
8.2.30
8.2.31
8.2.32
8.2.33
8.2.34
8.2.35
8.2.36
8.2.37
8.2.38
8.2.39
8.2.40
8.2.41
8.2.42
8.2.43
8.2.44
8.2.45
8.2.46
8.2.47
8.2.48
8.2.49
8.2.50
Page Program with 4-Byte Address (12h) .......................................................................... 51
Quad Input Page Program (32h) ........................................................................................ 52
Quad Input Page Program with 4-Byte Address (34h) ....................................................... 53
Sector Erase (20h) ............................................................................................................. 54
Sector Erase with 4-Byte Address (21h)............................................................................. 55
32KB Block Erase (52h) ..................................................................................................... 56
64KB Block Erase (D8h) ..................................................................................................... 57
64KB Block Erase with 4-Byte Address (DCh) ................................................................... 58
Chip Erase (C7h / 60h) ....................................................................................................... 59
Erase / Program Suspend (75h) ......................................................................................... 60
Erase / Program Resume (7Ah) ......................................................................................... 61
Power-down (B9h) .............................................................................................................. 62
Release Power-down / Device ID (ABh) ............................................................................. 63
Read Manufacturer / Device ID (90h) ................................................................................. 64
Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 65
Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 66
Read Unique ID Number (4Bh)........................................................................................... 67
Read JEDEC ID (9Fh) ........................................................................................................ 68
Read SFDP Register (5Ah) ................................................................................................ 69
Erase Security Registers (44h) ........................................................................................... 70
Program Security Registers (42h) ...................................................................................... 71
Read Security Registers (48h) ........................................................................................... 72
Individual Block/Sector Lock (36h) ..................................................................................... 73
Individual Block/Sector Unlock (39h) .................................................................................. 74
Read Block/Sector Lock (3Dh) ........................................................................................... 75
Global Block/Sector Lock (7Eh) .......................................................................................... 76
Global Block/Sector Unlock (98h) ....................................................................................... 76
Enable Reset (66h) and Reset Device (99h) ...................................................................... 77
9.
ELECTRICAL CHARACTERISTICS ............................................................................................... 78
9.1
Absolute Maximum Ratings (1) .......................................................................................... 78
9.2
9.3
Operating Ranges............................................................................................................... 78
Power-up Power-down Timing and Requirements ............................................................. 79
9.3.1
Power Cycle Requirement .................................................................................................... 80
DC Electrical Characteristics .......................................................................................................... 81
9.4
9.5
9.6
9.7
9.8
9.9
10.
AC Measurement Conditions .............................................................................................. 82
AC Electrical Characteristics
(4,5)
......................................................................................... 83
AC Electrical Characteristics (cont’d) .............................................................................. 84
Serial Output Timing ........................................................................................................... 85
Serial Input Timing .............................................................................................................. 85
/WP Timing ......................................................................................................................... 85
PACKAGE SPECIFICATIONS ........................................................................................................ 86
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W25Q256JW
10.1
10.1
10.2
10.3
10.4
10.5
10.6
10.7
11.
16-Pin SOIC 300-mil (Package Code F) ............................................................................ 86
8-Pad WSON 6x5-mm (Package Code P) ......................................................................... 87
8-Pad WSON 8x6-mm (Package Code E) ......................................................................... 88
24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) ........................................... 89
24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array) .............................................. 90
32-Ball WLCSP (Package Code Y, Ball pitch:0.50mm) ..................................................... 91
Ordering Information ........................................................................................................... 92
Valid Part Numbers and Top Side Marking ........................................................................ 93
REVISION HISTORY ...................................................................................................................... 94
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Publication Release Date: September 04, 2018
- Revision D
