W39F010
128K
×
8 CMOS FLASH MEMORY
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PIN CONFIGURATIONS ............................................................................................................ 4
BLOCK DIAGRAM ...................................................................................................................... 5
PIN DESCRIPTION..................................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................... 7
6.1
Device Bus Operation..................................................................................................... 7
6.1.1
6.1.2
6.1.3
6.1.4
Read Mode ...............................................................................................................7
Write Mode ...............................................................................................................7
Standby Mode ..........................................................................................................7
Output Disable Mode ................................................................................................7
6.2
6.3
Data Protection ............................................................................................................... 7
Boot Block Operation...................................................................................................... 8
6.3.1
6.3.2
6.3.3
6.3.4
Low VDD Inhibit ........................................................................................................8
Write Pulse "Glitch" Protection .................................................................................8
Logical Inhibit............................................................................................................8
Power-up Write Inhibit ..............................................................................................8
Read Command .......................................................................................................9
Auto-select Command ..............................................................................................9
Byte Program Command ..........................................................................................9
Chip Erase Command ............................................................................................10
Page Erase Command ...........................................................................................10
DQ7: Data Polling...................................................................................................10
DQ6: Toggle Bit ......................................................................................................11
6.4
Command Definitions ..................................................................................................... 8
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
Write Operation Status ................................................................................................. 10
6.5.1
6.5.2
7.
TABLE OF OPERATING MODES ............................................................................................ 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Device Bus Operations ................................................................................................. 12
Command Definitions ................................................................................................... 12
Embedded Programming Algorithm ............................................................................. 14
Embedded Erase Algorithm.......................................................................................... 15
Embedded #Data Polling Algorithm.............................................................................. 16
Boot Block Lockout Enable Flow Chart ........................................................................ 17
Software Product Identification and Boot Block Lockout Detection Flow Chart........... 18
-1-
Publication Release Date: December 26, 2005
Revision A4
W39F010
8.
DC CHARACTERISTICS.......................................................................................................... 19
8.1
8.2
8.3
9.
9.1
9.2
9.3
9.4
9.5
9.6
10.
10.1
10.2
10.3
10.4
10.5
10.6
10.7
11.
12.
13.
Absolute maximum Ratings .......................................................................................... 19
DC Operating Characteristics....................................................................................... 19
Pin Capacitance............................................................................................................ 19
AC Test Conditions....................................................................................................... 20
AC Test Load and Waveform ....................................................................................... 20
Read Cycle Timing Parameters.................................................................................... 21
Write Cycle Timing Parameters.................................................................................... 21
Power-up Timing........................................................................................................... 22
Data Polling and Toggle Bit Timing Parameters .......................................................... 22
Read Cycle Timing Diagram......................................................................................... 23
#WE Controlled Command Write Cycle Timing Diagram............................................. 23
#CE Controlled Command Write Cycle Timing Diagram.............................................. 24
Chip Erase Timing Diagram ......................................................................................... 24
Page Erase Timing Diagram ........................................................................................ 25
#DATA Polling Timing Diagram .................................................................................... 25
Toggle Bit Timing Diagram ........................................................................................... 26
AC CHARACTERISTICS .......................................................................................................... 20
TIMING WAVEFORMS ............................................................................................................. 23
ORDERING INFORMATION .................................................................................................... 27
HOW TO READ THE TOP MARKING...................................................................................... 28
PACKAGE DIMENSIONS ......................................................................................................... 29
13.1
13.2
13.3
13.4
32-pin P-DIP ................................................................................................................. 29
32-pin TSOP (8 x 20 mm)............................................................................................. 30
32-pin PLCC ................................................................................................................. 31
32-pin STSOP (8 x 14 mm) .......................................................................................... 31
14.
VERSION HISTORY ................................................................................................................. 32
-2-
W39F010
1. GENERAL DESCRIPTION
The
W39F010
is a 1Mbit, 5-volt only CMOS flash memory organized as 128K
×
8 bits. For flexible
erase capability, the 1Mbits of data are divided into 32 small even pages with 4 Kbytes. The byte-wide
(× 8) data appears on DQ7
−
DQ0. The device can be programmed and erased in-system with a
standard 5V power supply. A 12-volt V
PP
is not required. The unique cell architecture of the W39F010
results in fast program/erase operations with extremely low current consumption (compared to other
comparable 5-volt flash memory products). The device can also be programmed and erased by using
standard EPROM programmers.
2.
−
−
−
−
−
−
FEATURES
Single 5-volt operations
5-volt Read
5-volt Erase
5-volt Program
Byte-by-Byte programming: 50
μS
(max.)
Chip Erase cycle time: 100 mS (max.)
Page Erase cycle time: 25 mS (max.)
Fast Program operation:
Fast Erase operation:
Read access time: 70/90 nS
32 even pages with 4K bytes
Any individual page can be erased
Hardware protection:
−
Optional 16K byte Top/Bottom Boot Block with lockout protection
Flexible 4K-page size can be used as Parameter Blocks
Typical program/erase cycles:
−
1K/10K
Twenty-year data retention
Low power consumption
−
−
−
Active current: 15 mA (typ.)
Standby current: 15
μA
(typ.)
Software method: Toggle bit/Data polling
End of program detection
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin 600 mil DIP, 32-pin PLCC, 32- pin STSOP (8 x 14 mm) and 32- pin
TSOP
-3-
Publication Release Date: December 26, 2005
Revision A4
W39F010
3. PIN CONFIGURATIONS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
V
DD
#WE
NC
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-pin
DIP
26
25
24
23
22
21
20
19
18
17
A
1
2
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
14
A
1
5
3
A
1
6
2
N
C
1
V
D
D
32
#
W
E
31
N
C
30
29
28
27
A14
A13
A8
A9
A11
#OE
A10
#CE
DQ7
32-pin
PLCC
26
25
24
23
22
21
15
16
17
18
19
20
D
Q
1
D
Q
2
V
S
S
D
Q
3
D
Q
4
D
Q
5
D
Q
6
A11
A9
A8
A13
A14
NC
#WE
V
DD
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin
TSOP
#OE
A10
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
-4-
Publication Release Date: December 26, 2005
Revision A4
W39F010
4. BLOCK DIAGRAM
DQ
0
- DQ
7
VDD
Vss
Erase Voltage
Generator
Input / output
Buffers
#WE
State
Control
Command
Register
Program Voltage
Generator
#CE
#OE
VDD Detect
Timer
A
d
d
r
e
s
s
L
a
t
c
h
Chip Enable
Output Enable
Logic
Data
latch
Y-Decode
Y-MUX / SENSING
X-decode
ARRAY
A
0
- A
16
-5-
Publication Release Date: December 26, 2005
Revision A4
