White Electronic Designs
32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266, 333**, 400**
Package:
• 208 Plastic Ball Grid Array (PBGA),
13 x 22mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK
edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRanges
Organized as 32M x 64
• Can be user organized as 2x32Mx32 or
4x32Mx16
Weight: W3E32M64S-XSBX — 1.5 grams typical
W3E32M64S-XSBX
BENEFITS
73% Space Savings vs. FPBGA
• 43% Space Savings vs TSOP
Reduced part count
21% I/O reduction vs TSOP
• 13% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 64M x 64 density (contact factory
for information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
ar chi tec ture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
strobe transmitted by the DDR SDRAM during READs and
by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
**
For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature
CL = 3.
* This product is subject to change without notice.
*** For 400Mbs operation at commercial or industrial temperature CL = 3.
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
November 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
DENSITY COMPARISONS
TSOP Approach (mm)
11.9
11.9
11.9
11.9
W3E32M64S-XSBX
Actual Size
W3E32M64S-XSBX
13
22
22.3
66
TSOP
66
TSOP
66
TSOP
66
TSOP
S
A
V
I
N
G
S
Area
I/O
Count
4 x 265mm
2
= 1060mm
2
4 x 66 pins = 264 pins
CSP Approach (mm)
10.0
60
FBGA
10.0
60
FBGA
10.0
60
FBGA
10.0
60
FBGA
286mm
2
208 Balls
Actual Size
W3E32M64S-XSBX
13
22
73%
21%
S
A
V
I
N
G
S
12.5
Area
I/O
Count
4 x 125mm
2
= 500mm
2
4 x 60 balls = 240 balls
286mm
2
208 Balls
43%
13%
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs
allows for concurrent operation, thereby providing high
effective bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
November 2005
Rev. 3
2
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initial-
ized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FIGURE 1 – PIN CONFIGURATION
T
OP
V
IEW
W3E32M64S-XSBX
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
V
CCQ
2
V
CC
3
V
SS
4
V
CCQ
5
V
CCQ
6
V
SS
7
V
CCQ
8
V
CCQ
9
V
SS
10 11
V
CC
V
SS
V
SS
NC1
NC2
NC3
NC4
CSB#
NC5
NC6
V
SS
V
CCQ
V
SS
NC7
NC8
NC9
NC10
CASB#
RASB#
DQ34
CK3
CK3#
V
SS
DQ35
DQ51
WEB#
CKEB
NC11
NC12
DQ50
DQ53
DQ37
CK2#
CK2
DQ52
DQ36
DQ33
NC13
NC(BA2)
NC(A15)
DQ39
LDQS2
LDQS3
DQ48
DQ32
LDM3
LDM2
DQ49
DQ43
DQ59
NC(A14)
DQ55
DQ58
DQ42
LDQS2#
LDQS3#
DQ38
DQ54
DQ60
DQ57
UMD2
V
SS
DQ63
DQ56
DQ40
DQ61
DQ45
UMD3
DQ44
DQ41
DQ46
DQ62
V
CC
UDQS2#
DQ47
UDQS2
UDQS3
UDQS3#
V
CCQ
A6
A10
A9
V
CC
V
SS
V
CCQ
A3
A12
NC(A13)
V
CC
V
SS
A0
A11
V
CCQ
V
SS
V
REF
V
SS
V
CCQ
A1
BA1
V
SS
V
CC
A2
A4
A8
V
CCQ
V
SS
V
CC
BA0
A5
A7
V
CCQ
UDQS1#
UDQS1
UDQS0
DQ15
UDQSO#
V
CC
DQ30
DQ14
DQ9
DQ12
UMD1
DQ13
DQ29
DQ8
DQ24
DQ31
V
SS
UDM0
DQ25
DQ28
DQ22
DQ6
LDQS1#
LDQS0#
DQ10
DQ26
DQ23
ODT
DQ27
DQ11
DQ17
LDM0
LDM1
DQ0
DQ16
LDQS1
LDQS0
DQ7
NC
NC
NC
DQ1
DQ4
DQ20
CK0
CK0#
DQ5
DQ21
DQ18
NC
NC
CKEA
WEA#
DQ19
DQ3
V
SS
CK1#
CK1
DQ2
RASA#
CASA#
NC
NC
NC
NC
V
SS
V
CCQ
V
SS
NC
NC
CSA#
NC
NC
NC
NC
V
SS
V
CCQ
V
SS
V
CC
V
SS
V
CCQ
V
CCQ
V
SS
V
CCQ
V
CCQ
V
SS
V
CC
V
SS
* pin J10 is reserved for signal A13 on future upgrades.
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
November 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FIGURE 2 FUNCTIONAL BLOCK DIAGRAM
W3E32M64S-XSBX
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to V
CC
and V
CCQ
simultaneously, and
then to V
REF
(and to the system V
TT
). V
TT
must be applied
after V
CCQ
to avoid device latch-up, which may cause
permanent damage to the device. V
REF
can be applied any
time after V
CCQ
but is expected to be nominally coincident
with V
TT
. Except for CKE, inputs are not recognized as
valid until after V
REF
is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after V
CC
is applied.
After CKE passes through V
IH
, it will transition to an
SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200μs delay prior
to applying an executable command.
Once the 200μs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cy cles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (t
RFC
must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
pa ram e ters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
WE
0
RAS
0
CAS
0
WE RAS CAS
V
REF
A
0-12
CLK
0
CLK
0
CKE
0
CS
0
DQML
0
DQMH
0
DQSL
0
DQSH
0
BA
0-1
CLK
CLK
CKE
CS
DQML
DQMH
DQSL
DQSH
WE
1
RAS
1
CAS
1
WE RAS CAS
V
REF
A
0-12
CLK
1
CLK
1
CKE
1
CS
1
DQML
1
DQMH
1
DQSL
1
DQSH
1
BA
0-1
CLK
CLK
CKE
CS
DQML
DQMH
DQSL
DQSH
WE
2
RAS
2
CAS
2
WE RAS CAS
V
REF
A
0-12
CLK
2
CLK
2
CKE
2
CS
2
DQML
2
DQMH
2
DQSL
2
DQSH
2
BA
0-1
CLK
CLK
CKE
CS
DQML
DQMH
DQSL
DQSH
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
32
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
47
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
16
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
31
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
V
REF
A
0-12
BA
0-1
U0
U1
U2
WE
3
RAS
3
CAS
3
WE RAS CAS
V
REF
A
0-12
CLK
3
CLK
3
CKE
3
CS
3
DQML
3
DQMH
3
DQSL
3
DQSH
3
BA
0-1
CLK
CLK
CKE
CS
DQML
DQMH
DQSL
DQSH
DQ
0
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
15
DQ
48
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
DQ
63
U3
November 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
W3E32M64S-XSBX
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Fig ure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most significant
column address for a given configuration); and by A3-Ai
when the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLL should always
November 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
