module consists of nine 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
PC2-3200
Clock Speed
CL-t
RCD
-t
RP
* Consult factory for availability
PC2-4200
266MHz
4-4-4
PC2-5300
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
200MHz
3-3-3
May 2007
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
V
REF
V
SS
DQ0
DQ4
V
SS
DQ5
DQ1
V
SS
DQS0#
DM0
DQS0
V
SS
V
SS
DQ6
DQ2
DQ7
DQ3
V
SS
V
SS
DQ12
DQ8
DQ13
DQ9
V
SS
V
SS
DM1
DQS1#
V
SS
DQS1
DQ14
V
SS
DQ15
DQ10
V
SS
DQ11
DQ20
V
SS
DQ21
DQ16
V
SS
DQ17
RESET#
V
SS
DM2
DQS2#
V
SS
DQS2
DQ22
V
SS
DQ23
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
DQ18
V
SS
DQ19
DQ28
V
SS
DQ29
DQ24
V
SS
DQ25
DM3
V
SS
V
SS
DQS3#
DQ30
DQS3
DQ31
V
SS
V
SS
DQ26
CB4
DQ27
CB5
V
SS
V
SS
CB0
DM8
CB1
V
SS
V
SS
CB6
DQS8#
CB7
DQS8
V
SS
V
SS
CB2
CKE0
CB3
NC
V
SS
NC
NC
V
CC
NC
A12
A11
A9
V
CC
A7
A8
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
V
CC
A6
A5
A4
A3
V
CC
A2
A1
V
CC
A0
A10/AP
BA1
BA0
V
CC
RAS#
WE#
V
CC
CS0#
CAS#
ODT0
NC
A13
V
CC
V
CC
NC
CK
NC
CK#
DQ32
V
SS
V
SS
DQ36
DQ33
DQ37
DQS4#
V
SS
DQS4
DM4
V
SS
V
SS
DQ34
DQ38
DQ35
DQ39
V
SS
V
SS
DQ40
DQ44
DQ41
DQ45
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
V
SS
V
SS
DQS5#
DM5
DQS5
V
SS
V
SS
DQ46
DQ42
DQ47
DQ43
V
SS
V
SS
DQ52
DQ48
DQ53
DQ49
V
SS
V
SS
DM6
DQS6#
V
SS
DQS6
DQ54
V
SS
DQ55
DQ50
V
SS
DQ51
DQ60
V
SS
DQ61
DQ56
V
SS
DQ57
DM7
V
SS
DQ62
DQS7#
V
SS
DQS7
DQ63
DQ58
SDA
V
SS
SCL
DQ59
SA1
V
CC
SPD
SA0
W3HG64M72EEU-PD4
ADVANCED
PIN NAMES
Pin Name
A0-A13
BA0, BA1
DQ0-DQ63
CB0-CB7
DM0-DM8
DQS0-DQS8
DQS0#-DQS8#
ODT0
CK, CK#
CKE0
CS0#
RAS#
CAS#
WE#
V
CC
RESET#
V
SS
SA0-SA1
SDA
V
REF
V
CCSPD
SCL
NC
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
Data-in mask
Data strobes
Data strobes negative
On-die termination control
Clock Input
Clock enable input
Chip select input
Row Address Strobe
Column Address Strobe
Write Enable
Core Power
PLL Output enable
Ground
SPD address
Serial Data Input/Output
Input/Output Reference
Serial EEPROM power supply
SPD Clock Input
Spare pins, No connect
May 2007
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
W3HG64M72EEU-PD4
ADVANCED
3Ω
CS0#
DQS0
DQS0#
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1#
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQS8#
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS7
DQS7#
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS5#
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DQS4#
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/RDQS CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Serial PD
SCL
WP A0
A1
A2
SA2
SDA
SA0 SA1
V
CCSPD
V
CC
V
REF
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
120Ω
3Ω
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
ODT0
BA0 - BA1 : DDR2 SDRAMs
A0 - A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
120Ω
V
SS
CK
CK#
RESET#
P
L
L
OE
CK: SDRAMs
CK#: SDRAMs
NOTE: All resistor values are 22 ohms ±5% unless otherwise specified.
May 2007
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
IN
, V
OUT
T
STG
Parameter
Voltage on V
CC
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage Temperature
W3HG64M72EEU-PD4
ADVANCED
Min
-0.5
-0.5
-55
Command/Address,
RAS#, CAS#, WE#,
-18
-18
-10
-5
-5
-18
Max
2.3
2.3
100
18
18
10
5
5
18
Units
V
V
°C
µA
µA
µA
µA
µA
µA
I
L
Input leakage current; Any input 0V<V
IN
<V
CC
; V
REF
input
0V,V
IN
,0.95V; Other pins not under test = 0V
CS#, CKE
CK, CK#
DM
DQ, DQS, DQS#
I
OZ
I
VREF
Output leakage current; 0V<V
IN
<V
CC
; DQs and ODT are disable
V
REF
leakage current; V
REF
= Valid V
REF
level
DC OPERATING CONDITIONS
All voltages referenced to V
SS
Parameter
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Symbol
V
CC
V
REF
V
TT
V
CCSPD
Min
1.7
0.49 x V
CC
V
REF
-0.04
1.7
Typical
1.8
0.50 x V
CC
V
REF
-
Max
1.9
0.51 x V
CC
V
REF
+0.04
3.6
Unit
V
V
V
V
Notes
3
1
2
Notes:
1
V
REF
is expected to equal V
CC/2
of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
V
REF
may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on V
REF
may not exceed +/-2 percent of V
REF
. This measurement is to be taken at the nearest V
REF
bypass capacitor.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
and must track variations in the DC level of V
REF
.
3. V
CCQ
of all IC's are tied to V
CC
.
OPERATING TEMPERATURE CONDITION
Parameter
Operating Case Temperature (Commercial)
Symbol
TOPER
Rating
0 to +85°C
Units
°C
Notes
1, 2
NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 - 85
°C, operation temperature range, all DRAM specification will be supported.
May 2007
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
INPUT DC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
Input High (Logic 1) Voltage
Input High (Logic 0) Voltage
Symbol
V
IH
(DC)
V
IL
(DC)
Min
V
REF
+ 0.125
-0.300
W3HG64M72EEU-PD4
ADVANCED
Max
V
CC
+ 0.300
V
REF
- 0.125
Unit
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
AC Input High (Logic 1) Voltage
DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage
DDR2-667
AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533
AC Input High (Logic 0) Voltage
DDR2-667
Symbol
V
IH
(AC)
V
IH
(AC)
V
IL
(AC)
V
IL
(AC)
Min
V
REF
+ 0.250
V
REF
+ 0.200
-
-
Max
-
-
V
REF
- 0.250
V
REF
- 0.200
Unit
V
V
V
V
May 2007
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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