W42C31-03
Spread Spectrum Frequency Timing Generator
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Generates a spread spectrum copy of the provided
input
• Integrated loop filter components
• Operates with a 5V supply
• Low power CMOS design
• Available in 8-pin SOIC (Small Outline Integrated
Circuit)
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Table 1. Frequency Spread Selection
W42C31-03
FS1
0
0
The W42C31-03 incorporates the latest advances in PLL
spread spectrum frequency synthesizer techniques. By fre-
quency modulating the output with a low-frequency carrier,
EMI is greatly reduced. Use of this technology allows systems
to pass increasingly difficult EMI testing without resorting to
costly shielding or redesign.
1
1
FS0
0
1
0
1
Oscillator
Input
Frequency
(MHz)
10 to 20
10 to 20
20 to 33
20 to 33
XTAL Input
Frequency
(MHz)
10 to 20
10 to 20
20 to 25
20 to 25
Output
Frequency
(MHz)
f
IN
±1.875%
f
IN
±1.0%
f
IN
±1.875%
f
IN
–2.0%
Overview
Simplified Block Diagram
5.0V
Pin Configuration
SOIC
W42C31-03
X1
XTAL
Input
X2
W42C31-03
Spread Spectrum
Output
(EMI suppressed)
X1
X2
GND
FS0
1
2
3
4
8
7
6
5
OE#
FS1
VDD
CLKOUT
5.0V
Oscillator or Reference
Input
W42C31-03
Spread Spectrum
Output
(EMI suppressed)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
September 28, 1999, rev. **
W42C31-03
Pin Definitions
Pin Name
CLKOUT
X1
Pin No.
5
1
Pin
Type
O
I
Pin Description
Output Modulated Frequency:
Frequency modulated copy of the unmodulated input
clock
Crystal Connection or External Reference Frequency Input:
This pin has dual
functions. It may either be connected to an external crystal, or to an external reference
clock.
Crystal Connection:
If using an external reference, this pin must be left unconnected.
Output Enable (Active LOW):
This pin three-states the output when HIGH. It has an
internal pull-down resistor.
Frequency Selection Bit 0:
This pin selects the frequency spreading characteristics.
Refer to
Table 1.
This pin has a pull-up resistor.
Frequency Selection Bit 1:
This pin selects the frequency range. Refer to
Table 1.
This pin has a pull-up resistor.
Power Connection:
Connected to 5V power supply.
Ground Connection:
This should be connected to the common ground plane.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed, the modula-
tion percentage may be varied.
Using frequency select bits (FS1:0 pins), various spreading
percentages can be chosen (see
Table 1).
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between ±0.5% and ±2.5% are most
common.
The W42C31 features the ability to select from various spread
spectrum characteristics. Selections specific to the
W42C31-03 are shown in
Table 1.
Other spreading character-
istics are available (see separate data sheets) or can be cre-
ated with a custom mask.
X2
OE#
FS0
FS1
VDD
GND
2
8
4
7
6
3
I
I
I
I
P
G
Functional Description
The W42C31-03 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in
Figure 1.
An
on-chip crystal driver causes the crystal to oscillate at its fun-
damental. The resulting reference signal is divided by Q and
fed to the phase detector. A signal from the VCO is divided by
P and fed back to the phase detector also. The PLL will force
the frequency of the VCO output signal to change until the
divided output signal and the divided reference signal match
at the phase detector input. The output frequency is then equal
to the ratio of P/Q times the reference frequency. The unique
feature of the Spread Spectrum Clock Generator is that a mod-
ulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre-
determined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
VDD
X1
XTAL
X2
Freq.
Divider
Q
Phase
Detector
Charge
Pump
CLKOUT
Σ
VCO
Post
Dividers
Modulating
Waveform
Crystal load
capacitors
as needed
Feedback
Divider
P
PLL
GND
Figure 1. System Block Diagram
2
W42C31-03
Spread Spectrum Frequency Timing
Generation
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in
Figure 2.
An EMI emission profile
of a clock harmonic is shown.
5dB/div
SSFTG
Typical Clock
Modulating Waveform
The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in
Figure 3.
The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
f
Center
±
X
MOD
% in the frequency spread selection table.
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
proach is f
MAX
–
X
MOD
%. Whenever this expression is used,
Cypress has taken care to ensure that f
MAX
will never be ex-
ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
Amplitude (dB)
Figure 2. Typical Clock and SSFTG Comparison
OE# Pin
An internal pull-down resistor defaults the chip into a mode in
which all outputs are active. If OE# goes HIGH, all outputs are
three-stated. The chip will not prevent short cycles in a transi-
tion from three-state to enabled.
90%
100%
10%
Contrast the typical clock EMI with the Cypress Spread Spec-
trum Frequency Timing Generation EMI. Notice the spike in
the typical clock. This spike can make systems fail quasi-peak
EMI testing. The FCC and other regulatory agencies test for
peak emissions. With spread spectrum enabled, the peak en-
ergy is much lower (at least 8 dB) because the energy is
spread out across a wider bandwidth.
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Frequency Shift
10%
20%
30%
40%
50%
60%
70%
80%
20%
30%
40%
50%
60%
70%
80%
90%
Time
Figure 3. Modulation Waveform Profile
3
100%
W42C31-03
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
Parameter
V
DD
, V
IN
T
STG
T
A
T
B
P
D
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability
Rating
–0.5 to +7.0
–65 to +150
0 to +70
–55 to +125
0.5
Unit
V
°C
°C
°C
W
DC Electrical Characteristics:
0°C < T
A
< 70°C, V
DD
= 5V ±10%
Parameter
I
DD
t
ON
V
IL
V
IH
V
OL
V
OH
I
IL
I
IH
I
OL
I
OH
C
I
C
L
R
P
Z
OUT
Description
Supply Current
Power Up Time
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
Load Capacitance (as seen
by XTAL)
Input Pull-Up Resistor
Clock Output Impedance
Note 1
Note 1
@ 0.4V, V
DD
= 5V
@ 2.4V, V
DD
= 5V
All pins except X1, X2
Pins X1, X2
[2]
17
500
20
24
24
7
2.5
–100
10
0.7V
DD
0.4
First locked clock cycle after
Power Good
Test Condition
Min
Typ
18
Max
32
5
0.15V
DD
Unit
mA
ms
V
V
V
V
µA
µA
mA
mA
pF
pF
kΩ
Ω
AC Electrical Characteristics:
T
A
= 0°C to +70°C, V
DD
= 5V±10%
Symbol
f
IN
f
OUT
t
R
t
F
t
OD
t
ID
t
JCYC
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle
Input Duty Cycle
Jitter, Cycle-to-Cycle
Harmonic Reduction
8
V
DD
, 15-pF load 0.8–2.4
V
DD
, 15-pF load 2.4–0.8
15-pF load
45
40
Test Condition
Input Clock
Min
10
10
2
2
Typ
Max
33
33
5
5
55
60
300
Unit
MHz
MHz
ns
ns
%
%
ps
dB
Notes:
1. Inputs FS1:0 have a pull-up resistor; Input OE# has a pull-down resistor.
2. Pins X1 and X2 each have a 34-pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 17 pF. If driving X1 with a
reference clock signal, the load capacitance will be 34 pF (typical).
4
W42C31-03
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in
Figure 4
should be used.
V
DD
decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V
DD
pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
W42C31-03
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V
DD
connection can be
made via a ferrite bead, as shown.
The 6-pF XTAL load capacitors can be used to raise the inte-
grated 17-pF capacitance up to a total load of 20 pF on the
crystal.
Recommended Board Layout
Figure 5
shows a recommended 2-layer board layout.
1
C1
6 pF
XTAL1
8
7
6
5
R1
C3
0.1 µF
VDD
Output
2
GND
3
4
C2
6 pF
5V System Supply
FB
C4
10 µF Tantalum
Figure 4. Recommended Circuit Configuration
C1, C2 =
XTAL load capacitors (optional; use
is not required for operation).
Typical value is 6 pF.
High frequency supply decoupling
capacitor (0.1-µF recommended).
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
Match value to line impedance
Ferrite Bead
Via To GND Plane
Optional Guard Ring for
XTAL Oscillator Circuitry
C3 =
C4 =
G
C1
R1 =
FB
=
=
G
G
C2
XTAL1
C3
G
G
R1
Clock Output
G
C4
Power Supply Input
(5V)
FB
G
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
W42C31
Document #: 38-00802
Freq. Mask
Code
03
Package
Name
G
Package Type
8-pin Plastic SOIC (150-mil)
5
