GENERAL DESCRIPTION
The W536XXXA, a member of
ViewTalk
family, is a high-performance 4-bit micro-controller (uC) with
built-in speech unit, melody unit and 64seg * 16 com LCD driver unit which includes internal regulator
,pump circuit and dedicated two pages LCD RAM. The 4-bit uC core contains dual clock source, 4-bit
ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and
8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with
maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to
512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation.
It is ideal for games, educational toys, remote controllers, watches, clocks and other application
products which incorporate both LCD display and speech.
TM
Body
Voice
I/O pad
W536030A
30 sec
4I/O,8I
(RA/RC/RD)
W536060A
W536090A
W536120A
60 sec
90 sec
120 sec
8I/O, 8I
8I/O, 8I , 8O
8I/O, 8I, 8O
(RA/RB/RC/RD) (RA/RB/RC/RD/RE/RF) (RA/RB/RC/RD/RE/RF
)
WDT
disable/Enable
Y
Y
Y
Y
(Mask Option)
Sub-clock
RC/XTAL mode
Y
Y
Y
Y
(Mask Option)
RD port shared as
serial bus
Y(1)
Y(1)
N
N (2)
(Mask Option)
Tri-state serial bus
Y
Y
N
N
(Mask Option) ( 3)
Cascaded Voice
ROM through
Y(1)
Y(1)
N
Y
serial bus (2)
(1) Share 3 pads of RD port (RD1/RDP, RD2/SPDATA and RD3/WRP)
(2) Dedicate serial bus 3 pads (RDP, SPDATA and WRP) to interface with W55XXX. Cascaded
Voice ROM can help to expand voice up to 512 sec by W55XXX chip.
(3) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this
mask option is disabled to get minimum power consumption in general.
FEATURES
•
Operating voltage: 2.4 volt ~ 5.5 volt
•
Watch dog disabled/enabled by mask option
•
Dual clock operating system
−
Main clock with RC/Crystal (400 KHz to 4 MHz)
−
Sub-clock with 32.768 KHz RC/Crystal by mask option
-1-
Publication Release Date: April 2000
Revision A6
•
Memory
−
Program ROM (P-ROM): 32K
×
20 (ROM Bank0, 1, 2)
−
Data RAM (W-RAM): 1.4K
×
4 bit
(RAM Bank 0 is 896 nibbles from 0:000 ~0:37F and 0:380~0:3FF are mapped to special register.
RAM Bank F is 512 nibbles from F:200 ~F:3FF either data RAM or dedicated to script kernel )
−
LCD RAM (L-RAM): 256× 4 bit
×
2 pages (RAM Bank1, 2 from 200~2FF)
•
Maximum 24 input/output pads
−
Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory
W55XXX interface @W536030A/060A)
−
Ports for output only: 8 pads (RE & RF port; W536090A/120A available only)
−
Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536060A/090A/120A
only)
•
Power-down mode
−
Hold mode (except for 32kHz oscillator)
−
Stop mode (including 32kHz oscillator and release by RD or RC port)
•
Eight types of interrupts
−
Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody)
−
Three external interrupts (Port RC, RD, RA)
•
One built-in 14-bit clock frequency divider circuit
•
Two built-in 8-bit programmable countdown timers
−
Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
−
Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0
•
Built-in 18/14-bit watchdog timer for system reset.
•
Powerful instruction sets
•
8-level subroutine (including interrupt) nesting
•
LCD driver unit capability
−
VLCD higher than (VDD-0.5V)
−
Built-in voltage regulator to V2 pad
−
64 seg
×
16 com
−
1/16 or 1/8 duty, 1/5 or 1/4 bias, internal pump circuit option by special register
−
COM 8~ 15 and SEG40~63 can be shared as general input/output by special register
−
Either uC ROM or voice ROM used as LCD picture
•
Speech function
−
Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030A/060A/090A/120A based on 5 bits
MDPCM algorithm
−
Voice ROM (V-ROM) available for uC data or LCD picture data.
−
Maximum 8*256 Label/Interrupt vector (voice section number) available
−
Provide two types of speech busy flag to either each GO or each trigger
−
Maximum up to 16M bits speech address capability interface with external memory W55XXX
through serial bus.
•
Melody function
−
Provide 1K notes (22bits/note) dedicated melody ROM
−
Provide two types of melody busy flag to uC either each note or each song
−
Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7
−
Tremolo, triple frequency and 3 kinds of percussion available
−
Maximum 31 songs available
•
Can mix speech with melody
•
Multi-engine controller
•
Direct driving speaker/buzzer or DAC output
•
Chip On Board available
-2-
Publication Release Date:April 2000
Revision A6
BLOCK DIAGRAM
SEG0~63
COM0~15
V3,V4,V5,V6
V2
DH1,DH2
RAM
1.4*4Bit
LCD DRIVER
VDD
VLCD PUMP &
REGULATOR
VSS
PORT RA
ACC
TONE
RA0~3
ROM
32K*20Bit
ALU
PORT RB
RB0~3
PORT RC
RC0~3
PORT RD
PC
Special Register
IEF
STACK
(8 Levels)
HCF
FLAG1
LPX0
LPX4
HEF
SPC
PM0
LPX1
LPX5
PEF
MLD
MR0
LPX2
LPY0
EVF
FLAG0
PSR0
LPX3
LPY1
SPC_busy
SPC_play
LPXY
Shared_ROM Data
Speech
MDPCM
core
Parallel
to Serial
RD0~3
PORT RE
RE0~3
PORT RF
RF0~3
WRP
RDP
SPDATA
ROSC
VSSP
Timer 0
Timer 1
Interrupt ,Hold & Stop
Control
Voice ROM
(1M /2M/3M/4M bits)
MLD_busy
MLD_play
Watch Dog
Divide
Timing
Generator
Dual
Tone
melody
(1K notes)
PWM/DAC
Mix
Block
PWM1/DAC
PWM2
VDDP
TEST
RES
XIN XOUT X32I X32O
Publication Release Date:April 2000
Revision A6
-3-
PAD DESCRIPTION
SYMBOL
XIN/RXIN
I/O
I
FUNCTION
Input pad for main clock oscillator. It can be connected to crystal when crystal
mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate
main system clock while RC mode is selected (SCR0.2=0 and default). Oscillator
can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External
capacitor connects to start oscillation while crystal mode
Output pad for oscillator which is connected to another crystal pad when in crystal
mode. External capacitor connects to start oscillation when in crystal mode.
32.768 KHz crystal input pad or external resistor node 1
by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
32.768 KHz crystal output pad or external resistor node 2
by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
General Input/Output port specified by PM1 register. If output mode is selected,
PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special
register is set to logic 1. An interrupt source.
General Input/Output port specified by PM2 register. If output mode is selected,
PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode (W536060A/090A/120A only.)
4-bit sch
mitter input with internal pull high option specified by PM3 register bit 2. Each pad
has an independent interrupt capability specified by PEFL special register.
Interrupt and STOP mode wake up source. RC0 is also the external event
counter source of Timer1.
RD0
RD1/RDP
RD2/SPDATA
RD3/WRP
(4)
I
4-bit schmitter input port with internal pull high option specified by PM3 register
bit 3. Each pad has an independent interrupt capability specified by PEFH
special register. Interrupt and STOP mode wake up source. RD1~3 will be
shared as the external memory W55XXX interface pads while RD port shared as
serial bus mask option is enabled @W536030A/060A.
For W536030A/060A only, "Tri-state serial bus" mask option can use to float
WRP/RDP/SPDATD while "RD port shared as serial bus" mask option is
enabled.
RE0~RE3
RF0~RF3
O
O
I
Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving
capability option. (W536090A/120A only)
Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving
capability option. (W536090A/120A only)
System reset pad, active low with internal pull-high resistor.
Publication Release Date:April 2000
Revision A6
XOUT
X32I/RSUB1
O
I
X32O/RSUB2
O
RA0 ~ RA3/TONE
I/O
RB0 ~ RB3
I/O
RC0 ~ RC3
I
RES
-4-
TEST
ROSC
PWM1/DAC
PWM2
WRP (5)
RDP (5)
SPDATA (5)
SEG0−SEG39
SEG40/PORTN.0
SEG43/PORTN.3
SEG44/PORTM.0
SEG47/PORTM.3
SEG48/PORTL.0
SEG51/PORTL.3
SEG52/PORTK.0
SEG55/PORTK.3
SEG56/PORTJ.0
SEG59/PORTJ.3
SEG60/PORTI.0
SEG63/PORTI.3
I
I
O
O
O
O
I/O
O
O/O
Test pad. Active high with internal pull low resistor.
Connect resistor to VDD pad to generate speech or melody playing clock source.
While speech or melody is active , PWM1/DAC is speaker direct driving output
or DAC output controlled by voice output file.
While speech or melody is active, PWM2 is another speaker direct driving output.
External serial memory address write clock for voice extension (W536120A only).
External serial memory address read clock for voice extension. (W536120A only).
External serial memory data in/out for voice extension (W536120A only).
Dedicated LCD segment output pads.
LCD segment output pads, and can be shared as general output by register
LCDM3 bit 1. Default function is segment pad.
LCD segment output pads, and can be shared as general input by register
LCDM3 bit 0. Default function is segment pad and PM5.1=0 to inhibit LCD
waveform abnormal.
LCD segment output pads, and can be shared as general output by register
LCDM2 bit 0. Default function is segment pad.
LCD segment output pads, and can be shared as general input by register
LCDM2 bit 1. Default function is segment pad and PM5.0=0 to inhibit LCD
waveform abnormal.
LCD segment output pads, and can be shared as general input/output by register
LCDM2 bit 2. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.3=0 to inhibit LCD
waveform abnormal.
LCD segment output pads, and can be shared as general input/output by register
LCDM2 bit 3. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.2=0 to inhibit LCD
waveform abnormal.
O/I
O/O
O/I
O/IO
O/IO
-5-
Publication Release Date:April 2000
Revision A6
