W77E532/W77E532A DATA SHEET
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
GENERAL DESCRIPTION ......................................................................................................... 2
FEATURES ................................................................................................................................. 2
PIN CONFIGURATIONS ............................................................................................................ 3
PIN DESCRIPTION..................................................................................................................... 4
FUNCTIONAL DESCRIPTION ................................................................................................... 6
MEMORY ORGANIZATION ....................................................................................................... 8
INSTRUCTION.......................................................................................................................... 32
INSTRUCTION TIMING ............................................................................................................ 33
POWER MANAGEMENT.......................................................................................................... 41
INTERRUPTS ........................................................................................................................... 46
PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 49
SERIAL PORT .......................................................................................................................... 58
TIMED ACCESS PROTECTION .............................................................................................. 65
H/W REBOOT MODE (BOOT FROM 4K BYTES OF LDFLASH ) ........................................... 67
IN-SYSTEM PROGRAMMING ................................................................................................. 68
15.1 The Loader Program Locates at LDFLASH Memory ................................................... 68
15.2 The Loader Program Locates at APFLASH Memory ................................................... 68
H/W WRITER MODE ................................................................................................................ 68
SECURITY BITS ....................................................................................................................... 69
ELECTRICAL CHARACTERISTICS......................................................................................... 70
18.1 Absolute Maximum Ratings .......................................................................................... 70
18.2 DC Characteristics........................................................................................................ 70
18.3 AC Characteristics ........................................................................................................ 71
18.3.1 AC Specification ..........................................................................................................
72
18.3.2 MOVX Characteristics Using Strech Memory Cycle ....................................................
73
18.3.3 Program Memory Read Cycle .....................................................................................
74
18.3.4 Data Memory Read Cycle............................................................................................
75
18.3.5 Data Memory Write Cycle............................................................................................
75
TYPICAL APPLICATION CIRCUITS ........................................................................................ 76
19.1 Crystal connections ...................................................................................................... 76
19.2 Expanded External Data Memory and Oscillator ......................................................... 77
PACKAGE DIMENSIONS ......................................................................................................... 78
20.1 40-pin DIP ..................................................................................................................... 78
20.2 44-pin PLCC ................................................................................................................. 78
20.3 44-pin QFP.................................................................................................................... 79
APPLICATION NOTE ............................................................................................................... 80
REVISION HISTORY ................................................................................................................ 85
16.
17.
18.
19.
20.
21.
22.
-1-
Publication Release Date: November 19, 2007
Revision A9
W77E532/W77E532A
1. GENERAL DESCRIPTION
The W77E532A is a fast 8051 compatible microcontroller with a redesigned processor core without
wasted clock and memory cycles. As a result, it executes every 8051 instruction faster than the
original 8051 for the same crystal speed. Typically, the instruction executing time of W77E532A is 1.5
to 3 times faster then that of traditional 8051, depending on the type of instruction. In general, the
overall performance is about 2.5 times better than the original for the same crystal speed. Giving the
same throughput with lower clock speed, power consumption has been improved. Consequently, the
W77E532A is a fully static CMOS design; it can also be operated at a lower crystal clock. The
W77E532A contains In-System Programmable(ISP) 128 KB bank-addressed Flash EPROM; 4KB
auxiliary Flash EPROM for loader program; operating voltage from 4.5V to 5.5V; on-chip 1 KB MOVX
SRAM; three power saving modes.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit CMOS microcontroller
High speed architecture of 4 clocks/machine cycle runs up to 40 MHz
Pin compatible with standard 80C52
Instruction-set compatible with MCS-51
Four 8-bit I/O Ports; Port 0 has internal pull-up resisters enabled by software
One extra 4-bit I/O port, chip select and Wait State control signal (available on 44-pin PLCC/QFP
package)
Three 16-bit Timers
12 interrupt sources with two levels of priority
On-chip oscillator and clock circuitry
Two enhanced full duplex serial ports
Dual 64KB In-System Programmable Flash EPROM banks (APFLASH0 and APFLASH1)
4KB Auxiliary Flash EPROM for loader program (LDFLASH)
64 Bytes Non-Volatile Memory for critical date storage.
256 bytes scratch-pad RAM
1 KB on-chip SRAM for MOVX instruction
Programmable Watchdog Timer
Software Reset
Dual 16-bit Data Pointers
Software programmable access cycle to external RAM/peripherals
Packages:
−
Lead Free(RoHS) DIP 40:
W77E532A40DL
−
Lead Free(RoHS) PLCC 44: W77E532A40PL
−
Lead Free(RoHS) QFP 44: W77E532A40FL
-2-
Publication Release Date: November 19, 2007
Revision A9
W77E532/W77E532A
3. PIN CONFIGURATIONS
40-Pin DIP
T2, P1.0
T2EX, P1.1
RXD1, P1.2
TXD1, P1.3
INT2, P1.4
INT3, P1.5
INT4, P1.6
INT5, P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
44-Pin PLCC
I
N
T
2
,
P
1
.
4
T
X
D
1
,
P
1
.
3
R
X
D
1
,
P
1
.
2
T
2
E
X
,
P
1
.
1
44-Pin QFP
I
N
T
2
,
P
1
.
4
T
X
D
1
,
P
1
.
3
R
X
D
1
,
P
1
.
2
T
2
E
X
,
P
1
.
1
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
T
2
,
P
1
.
0
P
4 V
. D
2 D
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
1
2
T
2
,
P
1
.
0
P
4
.
2
V
D
D
INT3, P1.5
INT4, P1.6
INT5, P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V
S
S
P
4
.
0
,
/
W
A
I
T
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
INT3, P1.5
INT4, P1.6
INT5, P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
44 43 42 41 40 39 38 37 36 35 34
33
32
31
3
30
4
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V P
S 4
S .
0
,
/
W
A
I
T
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-3-
Publication Release Date: November 19, 2007
Revision A9
W77E532/W77E532A
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EA
I
EXTERNAL ACCESS ENABLE:
This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM
address and data will not be present on the bus if
EA
pin is high.
PROGRAM STORE ENABLE:
PSEN
enables the external ROM data onto the
Port 0 address/data bus during fetch and MOVC operations. When internal
ROM access is performed, no
PSEN
strobe signal outputs from this pin.
ADDRESS LATCH ENABLE:
ALE is used to enable the address latch that
separates the address from the data on Port 0.
RESET:
A high on this pin for two machine cycles while the oscillator is running
resets the device.
CRYSTAL1:
This is the crystal oscillator input. This pin may be driven by an
external clock.
CRYSTAL2:
This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND:
Ground potential
POWER SUPPLY:
Supply voltage for operation.
PORT 0:
Port 0 is an open-drain bi-directional I/O port. This port also provides a
multiplexed low order address/data bus during accesses to external memory.
Port 0 has internal pull-up resisters enabled by software.
PORT 1:
Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
RXD1(P1.2): Serial port 2 RXD
PSEN
O
ALE
RST
XTAL1
XTAL2
V
SS
V
DD
P0.0
−
P0.7
O
I
I
O
I
I
I/O
P1.0
−
P1.7
I/O
TXD1(P1.3): Serial port 2 TXD
INT2(P1.4): External Interrupt 2
INT3
(P1.5): External Interrupt 3
INT4(P1.6): External Interrupt 4
INT5
(P1.7): External Interrupt 5
P2.0
−
P2.7
I/O
PORT 2:
Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
-4-
Publication Release Date: November 19, 2007
Revision A9
W77E532/W77E532A
Pin Description, continued
SYMBOL
TYPE
DESCRIPTIONS
PORT 3:
Port 3 is a bi-directional I/O port with internal pull-ups. All bits have
alternate functions, which are described below:
RXD(P3.0) : Serial Port 0 input
TXD(P3.1) : Serial Port 0 output
INT0
(P3.2) : External Interrupt 0
P3.0
−
P3.7
I/O
INT1
(P3.3) : External Interrupt 1
T0(P3.4)
T1(P3.5)
: Timer 0 External Input
: Timer 1 External Input
WR
(P3.6) : External Data Memory Write Strobe
RD
(P3.7) : External Data Memory Read Strobe
P4.0
−
P4.3
I/O
PORT 4:
Port 4 is a 4-bit bi-directional I/O port. The P4.0 also provides the
alternate function
WAIT
which is the wait state control signal. The P4.3 also
provides the alternate function
REBOOT which is H/W reboot from LD flash.
* Note: TYPE
I : input, O: output, I/O: bi-directional.
-5-
Publication Release Date: November 19, 2007
Revision A9
测试/测量
