W91F840N SERIES
23-FLASH MEMORY TONE/PULSE DIALER WITH
HANDFREE, LOCK AND HOLD FUNCTIONS
GENERAL DESCRIPTION
The W91F840N is a series of tone/pulse switchable telephone dialers with 23-flash memory, keytone,
two store key function, hold, lock, mute, volume control and handfree dialing control features. These
chips are fabricated using Winbond's high-performance CMOS technology and thus offer good
performance in low-voltage, low-power operations.
FEATURES
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Tone/pulse switchable dialer
Two by 32 digits redial and save memory
Three by 32 digits one-touch direct repertory flash-memory
Twenty by 32 digits one-touch direct or two-touch indirect repertory flash-memory
4
The read-write times: 10
Pulse-to-tone (*/T) keypad for long distance call operation
Chain dialing
Uses 6
×
6 or 7
×
7 keyboard
Easy operation with redial, flash, pause, and */T keypads
Pause, P→T (pulse-to-tone) can be stored as a digit in memory
Dialing rate: 10 or 20 ppS by mask option
Minimum tone output duration: 93 mS
Minimum intertone pause: 93 mS
Pause time: 3.6 sec.
Two store key function. (S1 and S2)
Flash break time (100 mS, 300 mS, or 600 mS) selectable by keypad; pause time is 1.0 S
Make/break ratio (2:3 or 1:2) selectable by MODE pin
Mute key for speech network mute
No key will be accepted except the "HOLD" key when in the Hold mode
4-level volume control by V1 and V2 pin - default value is zero
Key tone output for valid keypad entry recognition
On-chip power-on reset
Uses 3.579545 MHz crystal or ceramic resonator
22-pin 400 mil, 24-pin 600 mil or 28-pin 600 mil dual-in-line plastic package
The different dialers in the W91F840N series are shown in the following table:
TYPE NO.
W91F840N
W91F840AN
W91F840LN
W91F840ALN
W91F841AN
W91F841ALN
W91F842N
W91F842AN
PULSE
(ppS)
10
10
10
10
10
10
20
20
FLASH-MEMORY
13 one touch, 10 two touch
13 one touch, 10 two touch
13 one touch, 10 two touch
13 one touch, 10 two touch
23 one touch
23 one touch
13 one touch, 10 two touch
13 one touch, 10 two touch
23 one touch
LOCK
-
-
√
√
KEY
TONE
√
√
HANDFREE
DIALING
-
√
-
-
√
-
√
√
√
VOLUME
CONTROL
-
-
-
-
√
√
-
√
-
√
√
-
-
-
√
-
-
PACKAGE
(PINS)
22
24
22
24
28
28
22
24
W91F843AN
20
-
√
√
√
28
-1-
Publication Release Date: July 1999
Revision A2
W91F840N SERIES
PIN CONFIGURATIONS
C1
C2
C1
C1
C2
C3
C4
C5
KT
H/P MUTE
V
SS
XT
XT
T/P MUTE
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
R6
R4
R3
R2
R1
K MUTE
V
DD
MODE
DTMF
DP
HKS
C2
C3
C4
C5
KT
H/P MUTE
V
SS
XT
XT
T/P MUTE
HFI
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
R6
R4
R3
R2
R1
K MUTE
V
DD
MODE
DTMF
XT
DP
T/P MUTE
HKS
HFO
HFI
V1
C3
C4
C5
C6
KT
H/P MUTE
V
SS
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R7
R6
R4
R3
R2
R1
K MUTE
V
DD
MODE
DTMF
DP
HKS
HFO
V2
W91F840N/F842N
W91F840AN/F842AN
W91F841AN/F843AN
C1
C2
C1
C1
C2
C3
C4
C5
LOCK
H/P MUTE
V
SS
XT
XT
T/P MUTE
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
R6
R4
R3
R2
R1
K MUTE
V
DD
MODE
DTMF
DP
HKS
C2
C3
C4
C5
LOCK
H/P MUTE
V
SS
XT
XT
T/P MUTE
HFI
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
R6
R4
R3
R2
R1
K MUTE
V
DD
MODE
DTMF
XT
DP
T/P MUTE
HKS
HFI
HFO
V1
C3
C4
C5
C6
LOCK
H/P MUTE
V
SS
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R7
R6
R4
R3
R2
R1
K MUTE
V
DD
MODE
DTMF
DP
HKS
HFO
V2
W91F840LN
W91F840ALN
W91F841ALN
-2-
W91F840N SERIES
PIN DESCRIPTION
SYMBOL
Column-
Row
Inputs
22-PIN
1−5
&
18−22
24-PIN
1−5
&
20−24
28-PIN
1−6
&
23−28
I/O
I
FUNCTION
The keyboard input is compatible with a standard 6
×
6 or 7
×
7 keyboard, an inexpensive single
contact (Form A) keyboard, and electronic input.
In normal operation, any single button can be
pushed to produce dual tone, pulses, or functions.
Activation of two or more buttons will result in no
response except for a single tone.
XT
9
9
10
I
A built-in inverter together with an inexpensive
3.579545 MHz crystal supplies the oscillator. The
oscillator stops when there is no keypad input. The
crystal frequency deviation is 0.02%.
Crystal oscillator output pin.
The T/P
MUTE
is a conventional CMOS N-channel
open drain output.
The output transistor turns on with a low level
during a dialing sequence (both pulse and tone
mode). Otherwise, it is off.
K
MUTE
17
19
22
O
The K
MUTE
is a conventional CMOS N-channel
open drain output.
Toggle action speech mute control pin by MUTE
key.
Connecting the mode pin to V
SS
places the dialer
in tone mode.
Connecting the mode pin to V
DD
places the dialer
in pulse mode with an M/B ratio of 40:60.
Leaving the mode pin floating places the dialer in
pulse mode with an M/B ratio of 33.3:66.7.
HKS
12
14
17
I
The
HKS
(hook switch) input is used to sense
whether the handset is on-hook or off-hook.
In on-hook state, HKS = 1: chip is in sleeping
mode, no operation.
In off-hook state,
HKS
= 0: chip is enabled for
normal operation.
HKS
pin is pulled to V
DD
by internal resistor.
KT
(W91F840N/F8
40AN/F842N/F
842AN/F841AN
/F843AN only)
XT
10
11
10
11
11
12
O
O
T/P
MUTE
MODE
15
17
20
I
6
6
7
O
The key tone output is a conventional CMOS
inverter. The key tone is generated when any valid
key is pressed; the KT pin generates a 1.2 KHz
square wave at 35 mS. When no key is pressed,
the KT pin remains in low state.
-3-
Publication Release Date: July 1999
Revision A2
W91F840N SERIES
Pin Description, continued
SYMBOL
LOCK
(W91F840LN/
F840ALN/
F841ALN only)
22-PIN
6
24-PIN
6
28-PIN
7
I/O
I
FUNCTION
The function of this terminal is to prevent "0"
dialing and "9" dialing under PABX system long
distance call control. When the first key input after
reset is 0 or 9, all key inputs, including the 0 or 9
key, become invalid and the chip generates no
output. The telephone is reinitialized by a reset.
The function of the LOCK pin is shown below:
LOCK PIN
V
DD
Floating
V
SS
FUNCTION
"0", "9" dialing inhibited
Normal dialing Mode
"0" dialing inhibited
H/P MUTE
7
7
8
I
The H/P MUTE is a conventional inverter output.
During pulse dialing, flash break or hold period, this
output is active high; otherwise, it remains in low
state.
N-channel open drain dialing pulse output.
Flash key will cause
DP
to be active in either tone
mode or pulse mode.
The timing diagram for pulse mode is shown in
Figure 1(a, b).
DP
13
15
18
O
DTMF
14
16
19
O
During pulse dialing, this pin remains in a low state
regardless of the keypad input. In tone mode, it will
output a dual or single tone.
A detailed timing diagram for tone mode is shown in
Figure 2(a, b).
OUTPUT FREQUENCY
Specified
R1
R2
R3
R4
C1
C2
C3
697
770
852
941
1209
1336
1477
Actual
699
766
848
948
1216
1332
1472
Error %
+0.28
-0.52
-0.47
+0.74
+0.57
-0.30
-0.34
V
DD
, V
SS
16, 8
18, 8
21, 9
I
Power input pins for the dialer chip. V
DD
is the
power and V
SS
is the ground.
-4-
W91F840N SERIES
Pin Description, continued
SYMBOL
V1, V2
22-PIN
-
24-PIN
-
28-PIN
14, 15
I/O
O
FUNCTION
Volume control output pins. These two pins can be
toggled by the volume control keys (Vup, Vdown).
These two pins output is a conventional CMOS N-
channel open drain output.
A low pulse on the HFI input pin toggles the
handfree control state. The status of the handfree
control state is listed in the following table:
CURRENT STATE
HOOK SW.
HFO
INPUT
HFI , HFO
-
12, 13
13, 16
I, O Handfree control pins.
NEXT STATE
HFO
DIALING
-
On Hook
Off Hook
On Hook
Off Hook
Off Hook
Low
High
High
-
Low
High
HFI
HFI
HFI
Off Hook
On Hook
On Hook
High
Low
Low
Low
Low
High
Yes
No
Yes
Yes
No
Yes
The HFI pin is pulled to V
DD
by an internal resistor.
A detailed timing diagram is shown in Figure 3.
BLOCK DIAGRAM
XT
XT
HKS
HFI
SYSTEM CLOCK
GENERATOR
ROW
(R1 ~ R7)
KEYBOARD
INTERFACE
COLUMN
(C1 ~ C6)
LOCATION
LATCH
READ/WRITE
COUNTER
CONTROL
LOGIC
LOCK
MODE
T/P MUTE
KT
RAM
PULSE
CONTROL
LOGIC
DP
HFO
H/P MUTE
K MUTE
V1
V2
DTMF
D/A
CONVERTER
ROW & COLUMN
PROGRAMMABLE
COUNTER
DATA LATCH
& DECODER
-5-
Publication Release Date: July 1999
Revision A2
