Preliminary W9330F
CODE DIVISION SPREAD SPECTRUM
TELEPHONE CHIP
GENERAL DESCRIPTION
The Winbond W9330F is an integrated 900 MHz cordless telephone controller. It employs Code
Division Spread Spectrum (CD/SS) technology optimized for low cost, consumer applications while
providing the clarity, distance and security of digital spread spectrum communication.
Targeted as a single chip baseband solution, the W9330F incorporates all digital signal processing
(DSP) and system control functions for the RF module, voice codec and key pad interface, thus
freeing the MPU for other user oriented tasks. Using 1-bit analog to digital conversion (ADC)
technique, signal processings are performed in an extended time domain transformation to allow for
the use of low cost radio modules. Linear RF coding schemes such as FSK, BPSK and MSK are
supported.
Advance built in features include acoustic echo minimization, data encryption, and diversity antenna
control. A proprietary noise reduction scheme can be implemented to correct for low speed multipath
fading found in consumer cordless and wireless local loop applications.
The W9330F is implemented in a low power 3V CMOS process technology. It is contained in a 100-
pin PQFP package. A complete reference design is available for telephone manufacturers for quick
turn development.
FEATURES
•
Low Cost Single Chip Baseband Cordless Telephone Solution
•
Advanced CD/SS digital signal processing architecture
•
FCC part-15 compliant for unlicensed 900 MHz and 2.4 GHz band operation
•
Optimized for low cost MPU and telephone components
•
Low Acoustic Echo
•
Support Multiple Handset Designs
•
Separate Command and Data Fields
•
22-bit User Selectable ID with Automatic Hardware Authentication
•
Audio Noise Reduction with Automatic Digital Noise Control
•
On-chip PLL, RF module and Codec Interface
•
Variable Rate CPU Clock Generation
•
Integrated Power Management
•
Hardware Supported Dual Antenna Design
•
Multi Clock Synchronization for Wireless Local Loop Applications
•
Built-in Data Encryption
•
3.0V Single Power Supply with 5.0V Tolerant I/O
•
Packaged in 100-pin PQFP/TQFP
-1-
Publication Release Date: August 1998
Revision A1
Preliminary W9330F
PIN CONFIGURATION
/
O W
R
S A
L L
C K /
O / G V A A A A / / G O O
E
E U E C N C D D D D W R N C C
N P A S D C 3 2 1 0 R D D K K
/
/
I A D C
R L E E E
Q E T R N
/
I
D
C
H
I
P
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AD4
AD5
AD6
AD7
VCC
GND
PA0
PA1
PA2
PA3
VCC
GND
PA4
PA5
PA6
PA7
GND
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
NC
NC
VCC
GND
PB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
W9330F
100-QFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
VCC
PD7
PD6
CPU_CLK
OSC_IN
OSC_OUT
GND
CLK_IN
CLK_OUT
GND
VCC
COD_SYNC
COD_CLK
DR
DT
BSYNC_OUT
BSYNC_IN
GND
VCC
PLL_SW
RF_PWR
TX_ENV
GND
TX_DATA
GND
RX_DATA
PD5
GND
VCC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P P P G P
B B B N B
1 2 3 D 4
P P P V G P
B B B C N D
5 6 7 C D 0
P P G V G R A P P
D D P C N E N D D
1 2 T C D S T 3 4
E S
T W
-2-
Preliminary W9330F
BLOCK DIAGRAM
CS
WR
RD
AD[7:0]
ALE
IRQ
DT
DR
COD_CLK
COD_SYN
CPU_CLK
OSC_EN
OSCI
OSCO
ID_DET
LOCK
RLOCK
CER
CHIP_EN
PA
uP
INTERFACE
PNA, B, C, D
PB
PC
PD
XMTR/
SPREADER
GENERAL
I/O
TX_DATA
RX_DATA
RF_PWR
PLL_SW
TX_ENV
ANTSW
RCVR/
DE-SPREADER
TDD_CTRL
RX
FIFO
TX
FIFO
PIN DESCRIPTIONS
The following table describes the external pins of the W9330F. The following conventions and
abbreviations are used in the signal descriptions:
Signal Name: All active low signals are indicated by overscore; otherwise the signal is active high.
Signal Type:
IN = 3V TTL input
IN_D = 3V TTL input with built-in pull down resister
IN_U = 3V TTL input with built-in pull up resister
OUT = 3V TTL output
OD = Open-drain 3V TTL output
IO = Bi-directional 3V TTL signal
-3-
Publication Release Date: August 1998
Revision A1
Preliminary W9330F
Table 1: Micro-controller Access Signals
PARAMETER
AD[7:0]
PIN
4, 3, 2,
1, 94,
93, 92,
91
84
TYPE
IO
DESCRIPTIONS
Address and data bus. This is the multiplexed address and
data bus used for micro-controller interface
ALE
IN
Address Latch Enable. Access address is latched at the falling
edge of the ALE. The address specifies the on-chip register
being accessed by the micro-controller.
Chip Select. This signal is asserted during a micro-controller
access cycle.
Interrupt Request. It is asserted by the W9330F to interrupt the
system micro-controller at certain operation points. Interrupt is
generated at the end of each transmit frame, the end of each
receive frame, and when frame error is detected.
Read Control. When
RD
is asserted, read data is driven on to
the AD[7:0] bus by the W9330F.
Write Control. When
WR
is asserted, write data on the AD[7:0]
bus is sampled by the W9330F.
CS
IRQ
97
85
IN
OUT
RD
WR
89
90
IN
IN
Table 2: Codec Interface
PARAMETER
COD_CLK
PIN
67
TYPE
OUT
DESCRIPTIONS
Codec transmit and receive clock. It is used by the Codec chip
to sample received data and generate transmit data. This
signal is generated from the main operating frequency and is
600 KHz.
Codec Synchronization signal. This is a 8 KHz framing clock
signal used by the Codec to synchronized transmit and receive
data. COD_SYNC is synchronous with COD_CLK and is
generated from the main operating frequency.
Received Data. Voice data to be sampled by the Codec. It is
sampled by the Codec chip at the falling edge of COD_CLK at
the beginning of each frame.
Transmit data. Voice data generated by the Codec for
transmission. It is generated by the Codec at the rising edge of
COD_CLK.
COD_SYNC
68
OUT
DR
66
OUT
DT
65
IN
-4-
Preliminary W9330F
Table 3: RF Module Interface
PARAMETER
ANTSW
PIN
48
TYPE
OUT
DESCRIPTIONS
Antenna Switch. This signal can be used to switch between two
available antenna in the system. The ANTSW signal changes
state only at the beginning of the gap time between frames.
Phase Lock Loop Switch. This signal switches the transceiver
phase lock loop between transmit and receive mode. PLL_SW is
high during transmission and the preceding gap time. It is low
when receiving.
RF Power. This signal switches the transmitter on and off during
full duplex operation. It is high when transmitting and low when
receiving. It is enveloped by TX_ENV to ensure the proper
timing sequence when the RF module switches direction.
Received Data. PN data recovered from the RF module. Input to
the de-spreader circuitry.
Transmit Data. Output of the spreader circuitry to be transmitted
by the RF module. TX_DATA is a high drive output but is not 5V
tolerant. All other external pins are 5V tolerant.
Transmitter Power. Switches the direction of the RF module. It is
high when transmitting and low when receiving. It envelopes
RF_PWR by 5.5 chip time in both edges.
PLL_SW
60
OUT
RF_PWR
59
OUT
RX_DATA
TX_DATA
54
56
IN
OUT
TX_ENV
58
OUT
Table 4: System Interface
PARAMETER
BSYNC_IN
PIN
63
TYPE
IN_D
DESCRIPTIONS
Burst Synchronization Input. This signal is designed to use in a
PBX setup where multiple master is located together. All the
BSYNC_IN signals should be connected together so that all
masters start transmission at the same time.
Burst Synchronization Output. This signal is designed to use in a
PBX setup where multiple master is located together. The
BSYNC_OUT of one master should be used as synchronization
source and connected to the BSYNC_IN to all masters, including
its own BSYNC_IN to synchronize transmission. If only one
master issused, the BSYNC_OUT should be connected to the
BSYNC_IN of the same device.
Chip Enable. This signal controls the internal clocks of the
device. When it is de-asserted, the internal clocks remain
unchanged (time freeze). The CPU_CLK signal and internal
timer are still operational while CHIP_EN is de-asserted. The
device is in operation mode only when CHIP_EN is asserted.
BSYNC_OUT
64
OUT
CHIP_EN
81
IN
-5-
Publication Release Date: August 1998
Revision A1
