W9412G2CB
1M
×
4 BANKS
×
32 BITS GDDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION .................................................................................................................................4
2. FEATURES ........................................................................................................................................................4
3. KEY PARAMETERS...........................................................................................................................................5
4. BALL CONFIGURATION....................................................................................................................................6
5. BALL DESCRIPTION .........................................................................................................................................7
6. BLOCK DIAGRAM..............................................................................................................................................9
7. FUNCTIONAL DESCRIPTION .........................................................................................................................10
7.1
7.2
Power Up Sequence............................................................................................................ 10
Command Function ............................................................................................................. 10
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
Bank Activate Command ......................................................................................................10
Bank Precharge Command ..................................................................................................10
Precharge All Command ......................................................................................................10
Write Command ...................................................................................................................10
Write with Auto-precharge Command ..................................................................................11
Read Command ...................................................................................................................11
Read with Auto-precharge Command ..................................................................................11
Mode Register Set Command ..............................................................................................11
Extended Mode Register Set Command ..............................................................................11
No-Operation Command ......................................................................................................11
Burst Read Stop Command..................................................................................................12
Device Deselect Command ..................................................................................................12
Auto Refresh Command .......................................................................................................12
Self Refresh Entry Command...............................................................................................12
Self Refresh Exit Command .................................................................................................12
Data Write Enable /Disable Command .................................................................................13
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Read Operation ................................................................................................................... 13
Write Operation ................................................................................................................... 13
Precharge ............................................................................................................................ 13
Burst Termination ................................................................................................................ 13
Refresh Operation ............................................................................................................... 14
Power Down Mode .............................................................................................................. 14
Input Clock Frequency Change during Precharge Power Down Mode .............................. 14
7.10.1
7.10.2
Burst Length field (A2 to A0) ................................................................................................15
Addressing Mode Select (A3)...............................................................................................15
7.10 Mode Register Operation .................................................................................................... 14
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Publication Release Date:Nov. 19, 2007
Revision A09
W9412G2CB
7.10.3
7.10.4
7.10.5
7.10.6
7.10.7
CAS Latency field (A6 to A4)................................................................................................16
DLL Reset bit (A8) ................................................................................................................16
Mode Register /Extended Mode register change bits (BA0, BA1) ........................................16
Extended Mode Register field ..............................................................................................17
Reserved field ......................................................................................................................17
8. OPERATION MODE.........................................................................................................................................18
8.1
8.2
8.3
8.4
8.5
8.6
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Simplified Truth Table.......................................................................................................... 18
Function Truth Table ........................................................................................................... 19
Function Truth Table, continued.......................................................................................... 20
Function Truth Table, continued.......................................................................................... 21
Function Truth Table for CKE.............................................................................................. 22
Simplified Stated Diagram................................................................................................... 23
Absolute Maximum Ratings................................................................................................. 24
Recommended DC Operating Conditions ........................................................................... 24
Capacitance......................................................................................................................... 25
Leakage and Output Buffer Characteristics ........................................................................ 25
DC Characteristics............................................................................................................... 26
AC Characteristics and Operating Condition....................................................................... 27
AC Test Conditions.............................................................................................................. 28
9. ELECTRICAL CHARACTERISTICS.................................................................................................................24
10. TIMING WAVEFORMS ....................................................................................................................................31
10.1 Command Input Timing ....................................................................................................... 31
10.2 Timing of the CLK Signals................................................................................................... 31
10.3 Read Timing (Burst Length = 4) .......................................................................................... 32
10.4 Write Timing (Burst Length = 4) .......................................................................................... 33
10.5 DM, DATA MASK (W9412G2CB) ....................................................................................... 34
10.6 Mode Register Set (MRS) Timing ....................................................................................... 35
10.7 Extend Mode Register Set (EMRS) Timing......................................................................... 36
10.8 Auto-precharge Timing (Read Cycle, CL = 2) ..................................................................... 37
10.9 Auto-precharge Timing (Read cycle, CL = 2), continued .................................................... 38
10.10 Auto-precharge Timing (Write Cycle) .................................................................................. 39
10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ................................................................ 40
10.12 Burst Read Stop (BL = 8) .................................................................................................... 40
10.13 Read Interrupted by Write & BST (BL = 8).......................................................................... 41
10.14 Read Interrupted by Precharge (BL = 8) ............................................................................. 41
10.15 Write Interrupted by Write (BL = 2, 4, 8) ............................................................................. 42
10.16 Write Interrupted by Read (CL = 2, BL = 8)......................................................................... 42
Publication Release Date:Nov. 19, 2007
Revision A09
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W9412G2CB
10.17 Write Interrupted by Read (CL = 3, BL = 4)......................................................................... 43
10.18 Write Interrupted by Precharge (BL = 8) ............................................................................. 43
10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ........................................................... 44
10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ........................................................... 44
10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ........................................................... 45
10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ........................................................... 45
10.23 Auto Refresh Cycle.............................................................................................................. 46
10.24 Precharge/Activate Power Down Mode Entry and Exit Timing ........................................... 46
10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................... 46
10.26 Self Refresh Entry and Exit Timing ..................................................................................... 47
11. PACKAGE SPECIFICATION............................................................................................................................47
11.1 144L LFBGA (12X12X1.40 mm^3, Ø=0.5mm).................................................................... 48
12. REVISION HISTORY .......................................................................................................................................49
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Publication Release Date:Nov. 19, 2007
Revision A09
W9412G2CB
1. GENERAL DESCRIPTION
W9412G2CB is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 1,048,576 words
×
4 banks
×
32 bits. Using pipelined architecture and 0.11 µm
process technology, W9412G2CB delivers a data bandwidth of up to 400M words per second (-5). To
fully comply with the personal computer industrial standard, W9412G2CB is sorted into following
speed grades: -5/-5H, -6 and -75. The -5/-5H is compliant to the DDR400/CL3 specification. The -6 is
compliant to the DDR333/CL2.5 specification. The -75 is compliant to the DDR266/CL2 specification.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and
CLK
signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9412G2CB is ideal for any high
performance applications.
2. FEATURES
•
2.5V
±0.2V
Power Supply for DDR266/333/400
•
Up to 200 MHz Clock Frequency
•
Double Data Rate architecture; two data transfers per clock cycle
•
Differential clock inputs (CLK and
CLK
)
•
DQS is edge-aligned with data for Read; center-aligned with data for Write
•
CAS Latency: 2, 2.5 and 3
•
Burst Length: 2, 4 and 8
•
Auto Refresh and Self Refresh
•
Precharged Power Down and Active Power Down
•
Write Data Mask
•
Write Latency = 1
•
15.6µS Refresh interval (4K/64 mS Refresh)
•
Maximum burst refresh cycle: 8
•
Interface: SSTL_2
•
Packaged in 144L LFBGA (12X12X1.40 mm^3, Ø=0.5mm), using Pb free with RoHS compliant
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Publication Release Date:Nov. 19, 2007
Revision A09
W9412G2CB
3. KEY PARAMETERS
SYMBOL
DESCRIPTION
CL = 2
t
CK
Clock Cycle Time
CL = 2.5
CL = 3
t
RAS
t
RC
Active to Precharge Command Period
Active to Ref/Active Command Period
Operating Current:
One Bank Active-Precharge
Operating Current:
One Bank Active-Read-Precharge
Burst Operation Read Current
Burst Operation Write Current
Auto Refresh Current
Self Refresh Current
MIN./MAX.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
-5/-5H
7.5 nS
12 nS
6 nS
12 nS
5 nS
10 nS
40 nS
50 nS
150 mA
170 mA
220 mA
250 mA
200 mA
3 mA
-6
7.5 nS
12 nS
6 nS
12 nS
6 nS
12 nS
42 nS
54 nS
140 mA
160 mA
200 mA
230 mA
190 mA
3 mA
-75
7.5 nS
12 nS
7.5 nS
12 nS
7.5 nS
12 nS
45 nS
60 nS
130 mA
150 mA
180 mA
210 mA
180 mA
3 mA
I
DD0
I
DD1
I
DD4R
I
DD4W
I
DD5
I
DD6
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Publication Release Date:Nov. 19, 2007
Revision A09
