W9412G6CH
2M
×
4 BANKS
×
16 BITS DDR SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES ................................................................................................................................. 4
KEY PARAMETERS ................................................................................................................... 5
PIN CONFIGURATION ............................................................................................................... 6
PIN DESCRIPTION..................................................................................................................... 7
BLOCK DIAGRAM ...................................................................................................................... 8
FUNCTIONAL DESCRIPTION.................................................................................................... 9
7.1
7.2
Power Up Sequence....................................................................................................... 9
Command Function ........................................................................................................ 9
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
Bank Activate Command ..........................................................................................9
Bank Precharge Command ......................................................................................9
Precharge All Command ..........................................................................................9
Write Command........................................................................................................9
Write with Auto-precharge Command.....................................................................10
Read Command .....................................................................................................10
Read with Auto-precharge Command ....................................................................10
Mode Register Set Command ................................................................................10
Extended Mode Register Set Command ................................................................10
No-Operation Command ........................................................................................10
Burst Read Stop Command....................................................................................11
Device Deselect Command ....................................................................................11
Auto Refresh Command .........................................................................................11
Self Refresh Entry Command .................................................................................11
Self Refresh Exit Command ...................................................................................11
Data Write Enable /Disable Command ...................................................................12
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Read Operation............................................................................................................. 12
Write Operation............................................................................................................. 12
Precharge ..................................................................................................................... 12
Burst Termination.......................................................................................................... 13
Refresh Operation......................................................................................................... 13
Power Down Mode ....................................................................................................... 13
Input Clock Frequency Change during Precharge Power Down Mode........................ 13
Mode Register Operation.............................................................................................. 14
7.10.1
Burst Length field (A2 to A0)...................................................................................14
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Publication Release Date:Nov. 19, 2007
Revision A07
W9412G6CH
7.10.2
7.10.3
7.10.4
7.10.5
7.10.6
7.10.7
Addressing Mode Select (A3) .................................................................................14
CAS Latency field (A6 to A4) ..................................................................................16
DLL Reset bit (A8) ..................................................................................................16
Mode Register/Extended Mode register change bits (BS0, BS1) ...........................16
Extended Mode Register field.................................................................................17
Reserved field.........................................................................................................17
8.
OPERATION MODE ................................................................................................................. 18
8.1
8.2
8.3
8.4
Simplified Truth Table................................................................................................... 18
Function Truth Table..................................................................................................... 19
Function Truth Table for CKE ....................................................................................... 22
Simplified Stated Diagram ............................................................................................ 23
Absolute Maximum Ratings .......................................................................................... 24
Recommended DC Operating Conditions .................................................................... 24
Capacitance .................................................................................................................. 25
Leakage and Output Buffer Characteristics.................................................................. 25
DC Characteristics ........................................................................................................ 26
AC Characteristics and Operating Condition................................................................ 27
AC Test Conditions....................................................................................................... 29
Table 1: Input Slew Rate for DQ, DQS, and DM .......................................................... 32
Table 2: Input Setup & Hold Time Derating for Slew Rate ........................................... 32
Table 3: Input/Output Setup & Hold Time Derating for Slew Rate ............................... 32
Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate................ 32
Table 5: Output Slew Rate Characteristics (X16 Devices only) ................................... 32
Table 6: Output Slew Rate Matching Ratio Characteristics ......................................... 33
Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins......... 33
Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins.......... 34
System Notes:............................................................................................................... 35
Command Input Timing ................................................................................................ 37
Timing of the CLK Signals ............................................................................................ 37
Read Timing (Burst Length = 4) ................................................................................... 38
Write Timing (Burst Length = 4).................................................................................... 39
DM, DATA MASK (W9412G6CH)................................................................................. 40
Mode Register Set (MRS) Timing................................................................................. 41
Extend Mode Register Set (EMRS) Timing .................................................................. 42
Publication Release Date:Nov. 19, 2007
Revision A07
9.
ELECTRICAL CHARACTERISTICS......................................................................................... 24
9.1
9.2
9.3
9.4
9.5
9.6
9.7
10.
SYSTEM CHARACTERISTICS FOR DDR SDRAM................................................................. 32
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11.
TIMING WAVEFORMS ............................................................................................................. 37
11.1
11.2
11.3
11.4
11.5
11.6
11.7
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W9412G6CH
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
11.23
11.24
11.25
11.26
12.
13.
12.1
Auto-precharge Timing (Read Cycle, CL = 2) .............................................................. 43
Auto-precharge Timing (Read cycle, CL = 2), continued ............................................. 44
Auto-precharge Timing (Write Cycle).......................................................................... 45
Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ........................................................ 46
Burst Read Stop (BL = 8) ............................................................................................ 46
Read Interrupted by Write & BST (BL = 8).................................................................. 47
Read Interrupted by Precharge (BL = 8) ..................................................................... 47
Write Interrupted by Write (BL = 2, 4, 8) ..................................................................... 48
Write Interrupted by Read (CL = 2, BL = 8) ................................................................ 48
Write Interrupted by Read (CL = 3, BL = 4) ................................................................ 49
Write Interrupted by Precharge (BL = 8) ..................................................................... 49
2 Bank Interleave Read Operation (CL = 2, BL = 2) ................................................... 50
2 Bank Interleave Read Operation (CL = 2, BL = 4) ................................................... 50
4 Bank Interleave Read Operation (CL = 2, BL = 2) ................................................... 51
4 Bank Interleave Read Operation (CL = 2, BL = 4) ................................................... 51
Auto Refresh Cycle ..................................................................................................... 52
Precharged/Active Power Down Mode Entry and Exit Timing .................................... 52
Input Clock Frequency Change during Precharge Power Down Mode Timing .......... 52
Self Refresh Entry and Exit Timing ............................................................................. 53
66L TSOP – 400 mil ..................................................................................................... 54
Package Specification............................................................................................................... 54
REVISION HISTORY ................................................................................................................ 55
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Publication Release Date: Nov. 19, 2007
Revision A07
W9412G6CH
1. GENERAL DESCRIPTION
W9412G6CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 2M words
×
4 banks
×
16 bits. Using pipelined architecture and 0.11µm
process technology, W9412G6CH delivers a data bandwidth of up to 444M words per second (-45).
To fully comply with the personal computer industrial standard, W9412G6CH is sorted into four speed
grades: -45, -5, -6 and -75 .The -45 is compliant to the DDR444/CL3 specification, the -5 is compliant
to the DDR400/CL3 specification, the -6 is compliant to the DDR333/CL2.5 specification and the -75 is
compliant to the DDR266/CL2 specification.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and
CLK
signals cross during a transition. Write and
Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9412G6CH is ideal for main memory in
high performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5V
±0.2V
Power Supply for DDR266
2.5V
±0.2V
Power Supply for DDR333
2.6V
±
5% Power Supply for DDR400
2.6V
±
5% Power Supply for DDR444
Up to 222 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and
CLK
)
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5 and 3
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
15.6µS Refresh interval (4K / 64 mS Refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant
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Publication Release Date:Nov. 19, 2007
Revision A07
W9412G6CH
3. KEY PARAMETERS
SYMBOL
DESCRIPTION
CL = 2
MIN./MAX.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
-45
-
-
-
-
4.5 nS
12 nS
36 nS
54 nS
130 mA
140 mA
180 mA
180 mA
200 mA
3 mA
-5
7.5 nS
12 nS
6 nS
12 nS
5 nS
12 nS
40 nS
50 nS
130 mA
140 mA
180 mA
180 mA
200 mA
3 mA
-6
7.5 nS
12 nS
6 nS
12 nS
6 nS
12 nS
42 nS
54 nS
120 mA
130 mA
170 mA
170 mA
190 mA
3 mA
-75
7.5 nS
12 nS
7.5 nS
12 nS
7.5 nS
12 nS
45 nS
60 nS
110 mA
120 mA
160 mA
160 mA
180 mA
3 mA
t
CK
Clock Cycle Time
CL = 2.5
CL = 3
t
RAS
t
RC
I
DD0
I
DD1
I
DD4R
I
DD4W
I
DD5
I
DD6
Active to Precharge Command Period
Active to Ref/Active Command Period
Operating Current:
One Bank Active-Precharge
Operating Current:
One Bank Active-Read-Precharge
Burst Operation Read Current
Burst Operation Write Current
Auto Refresh Current
Self Refresh Current
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Publication Release Date: Nov. 19, 2007
Revision A07
