W942504BH
16M
×
4 BANKS
×
4 BIT DDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ..................................................................................................................3
2. FEATURES ..........................................................................................................................................3
3. KEY PARAMETERS ............................................................................................................................3
4. PIN CONFIGURATION........................................................................................................................4
5. PIN DESCRIPTION .............................................................................................................................5
6. BLOCK DAIAGRAM.............................................................................................................................6
7. ABSOLUTE MAXIMUM RATINGS ......................................................................................................7
8. RECOMMENDED DC OPERATING CONDITIONS............................................................................7
9. CAPACITANCE ...................................................................................................................................8
10. LEAKAGE AND OUTPUT BUFFER CHARACTERISTICS ...............................................................8
11. DC CHARACTERISTICS...................................................................................................................9
12. AC CHARACTERISTICS AND OPERATING CONDITION.............................................................10
13. AC TEST CONDITIONS ..................................................................................................................11
14. OPERATION MODE ........................................................................................................................13
Simplified Truth Table............................................................................................................................ 13
Function Truth Table
(Note 1)
.................................................................................................................. 14
Function Truth Table for CKE................................................................................................................ 17
15. SIMPLIFIED STATE DIAGRAM ......................................................................................................18
16. FUNCTIONAL DESCRIPTION ........................................................................................................19
Power Up Sequence.............................................................................................................................. 19
Command Function ............................................................................................................................... 19
Read Operation ..................................................................................................................................... 22
Write Operation ..................................................................................................................................... 22
Precharge .............................................................................................................................................. 22
Burst Termination .................................................................................................................................. 22
Refresh Operation ................................................................................................................................. 23
Power Down Mode ................................................................................................................................ 23
Mode Register Operation ...................................................................................................................... 23
17. TIMING WAVEFORMS....................................................................................................................27
Command Input Timing ......................................................................................................................... 27
Timing of the CLK Signals ..................................................................................................................... 27
Read Timing (Burst Length = 4) ............................................................................................................ 28
Write Timing (Burst Length = 4)............................................................................................................. 29
-1-
Publication Release Date: March 12, 2002
Revision A1
W942504BH
Mode Register Set (MRS) Timing.......................................................................................................... 31
Extend Mode Register Set (EMRS) Timing ........................................................................................... 32
Auto Precharge Timing (Read Cycle, CL = 2) ....................................................................................... 33
Auto Precharge Timing (Write Cycle) .................................................................................................... 35
Read interrupted by Read (CL = 2, BL = 2, 4, 8)................................................................................... 36
Burst Read Stop (BL = 8) ...................................................................................................................... 36
Read Interrupted by Write & BST (BL = 8) ............................................................................................ 37
Read Interrupted by Precharge (BL = 8) ............................................................................................... 37
Write Interrupted by Write (BL = 2, 4, 8)................................................................................................ 38
Write Interrupted by Read (CL = 2, BL = 8)........................................................................................... 38
Write Interrupted by Read (CL = 2. 5, BL = 4)....................................................................................... 39
Write Interrupted by Precharge (BL = 8)................................................................................................ 39
2 Bank Interleave Read Operation (CL = 2, BL = 4).............................................................................. 40
4 Bank Interleave Read Operation (CL = 2, BL = 2).............................................................................. 41
4 Bank Interleave Read Operation (CL = 2, BL = 4).............................................................................. 41
Auto Refresh Cycle................................................................................................................................ 42
Active Power Down Mode Entry and Exit Timing .................................................................................. 42
Precharged Power Down Mode Entry and Exit Timing ......................................................................... 42
Self Refresh Entry and Exit Timing........................................................................................................ 43
18. PACKAGE DIMENSION ..................................................................................................................44
TSOP 66l - 400 mil ................................................................................................................................ 44
19. VERSION HISTORY........................................................................................................................45
-2-
W942504BH
1. GENERAL DESCRIPTION
W942504BH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 16,777,216 words
×
4 banks
×
4 bits. Using pipelined architecture and 0.175
µm
process technology, W942504BH delivers a data bandwidth of up to 286M words per second (-7).
To fully comply with the personal computer industrial standard, W942504BH is sorted into three speed
grades: -7, -75 and The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -75 is
compliant to the DDR266/CL2.5 specification.
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942504BH is ideal for main memory in
high performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5V
±0.2V
Power Supply
Up to 143 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential Clock Inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2 and 2.5
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
8K Refresh Cycles /64 mS
Interface: SSTL-2
Packaged in TSOP II 66-pin, 400 x 875 mil, 0.65 mm pin pitch
3. KEY PARAMETERS
SYMBOL
DESCRIPTION
MIN./MAX.
-7
-75
t
CK
t
RAS
t
RC
I
DD1
I
DD4
I
DD6
Clock Cycle Time
CL = 2
CL = 2.5
Min.
Min.
Min.
Min.
Max.
Max.
Max.
7.5 nS
7 nS
45 nS
65 nS
110 mA
165 mA
3 mA
8 nS
7.5 nS
45 nS
65 nS
110 mA
155 mA
3 mA
Active to Precharge Command Period
Active to Ref/Active Command Period
Operation Current (Single bank)
Burst Operation Current
Self-Refresh Current
-3-
Publication Release Date: March 12, 2002
Revision A1
W942504BH
4. PIN CONFIGURATION
V
DD
NC2
V
DD
Q
NC2
DQ0
V
SS
Q
NC2
NC2
V
DD
Q
NC2
DQ1
V
SS
Q
NC2
NC1
V
DD
Q
NC2
NC1
V
DD
NC1
NC2
WE
CAS
RAS
CS
NC1
BS0
BS1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
NC2
V
SS
Q
NC2
DQ3
V
DD
Q
NC2
NC2
V
SS
Q
NC2
DQ2
V
DD
Q
NC2
NC1
V
SS
Q
DQS
NC1
V
REF
V
SS
DM
CLK
CLK
CKE
NC1
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
-4-
W942504BH
5. PIN DESCRIPTION
PIN NUMBER
28
−
32,
35
−
42
26,27
5, 11, 56, 62
PIN NAME
A0
−
A12
FUNCTION
Address
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0
−
A12.
Column address: A0
−
A9, A11. (A10 is used for Auto Precharge)
Select bank to activate during row address latch time, or bank to
read/write during column address latch time.
BS0, BS1
DQ0
−
DQ3
DQS
Bank Select
Data Input/ The DQ0 – DQ7 input and output data are synchronized with both
Output
edges of DQS.
DQS is Bi-directional signal. DQS is input signal during write
Data Strobe operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
Disable or enable the command decoder. When command
Chip Select decoder is disabled, new command is ignored and previous
operation continues.
Command
Inputs
Write mask
Command inputs (along with
CS
) define the command being
entered.
When DM is asserted
"
high
"
in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
51
24
CS
23, 22, 21
47
45, 46
RAS
,
CAS
,
WE
DM
CLK,
CLK
Differential All address and control input signals are sampled on the crossing
clock inputs of the positive edge of CLK and negative edge of
CLK
.
CKE controls the clock activation and deactivation. When CKE is
Clock Enable low, Power Down mode, Suspend mode, or Self Refresh mode is
entered.
Reference
Voltage
Power
(+2.5V)
Ground
Power
(+2.5V) for
I/O buffer
Ground for
I/O buffer
V
REF
is reference voltage for inputs.
Power for logic circuit inside DDR SDRAM.
Ground for logic circuit inside DDR SDRAM.
Separated power from V
DD
, used for output buffer, to improve
noise.
Separated ground from V
SS
, used for output buffer, to improve
noise.
44
CKE
49
1, 18, 33
34, 48, 66
3, 9, 15, 55, 61
V
REF
V
DD
V
SS
V
DD
Q
6, 12, 52, 58, 64
2, 4, 7, 8, 10, 13,
14, 16, 17, 19,
20, 25, 43, 50,
53, 54, 57, 59,
60, 63, 65
V
SS
Q
NC1, NC2
No
No connection
Connection
-5-
Publication Release Date: March 12, 2002
Revision A1
